[S] Change in coreboot[main]: soc/intel/xeon_sp: Add SATC PCI segment group support

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu.

Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/81180?usp=email

to look at the new patch set (#6).

The following approvals got outdated and were removed:
Code-Review+2 by Shuo Liu, Verified+1 by build bot (Jenkins)

Change subject: soc/intel/xeon_sp: Add SATC PCI segment group support
......................................................................

soc/intel/xeon_sp: Add SATC PCI segment group support

For every PCI segment group generate a new SATC header.
Allows to generate proper ACPI code when multiple PCI segment
groups are enabled.

TEST: Booted on ibm/sbp1 with multiple PCI segment groups.
      Properly generates multiple SATC headers.

Change-Id: I93b8ee05a7e6798e034f7a5da2c6883f0ee7a0e5
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/uncore_acpi.c
1 file changed, 40 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/81180/6