[XS] Change in coreboot[main]: soc/intel/ptl: Disable FSP_UGOP_EARLY_SIGN_OF_LIFE for PTL

[Jayvik Desai (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Kapil Porwal, Pranava Y N, Subrata Banik.

Jayvik Desai has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/86314?usp=email )

Change subject: soc/intel/ptl: Disable FSP_UGOP_EARLY_SIGN_OF_LIFE for PTL
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Patch Set 2:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86314/comment/c0ed058a_1e3f1d68?usp... :
PS1, Line 9: Disable ESOL for PTL until the feature is ready and tested.
> nit ? […]

Acknowledged

https://review.coreboot.org/c/coreboot/+/86314/comment/839dbbf3_3a2f7ff0?usp... :
PS1, Line 11: BUG=none
> not needed

Acknowledged

https://review.coreboot.org/c/coreboot/+/86314/comment/fc9435c4_660f4259?usp... :
PS1, Line 12: emerge-fatcat coreboot
> Able to built and boot google/fatcat to OS.

Acknowledged

https://review.coreboot.org/c/coreboot/+/86314/comment/38528e01_f230c7ea?usp... :
PS1, Line 13: BRANCH=none
> not needed

Acknowledged