Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64867 )
Change subject: soc/amd/*: Move apm call out of MP init code ......................................................................
soc/amd/*: Move apm call out of MP init code
This makes it easier to have common code for MP init on AMD systems.
Change-Id: Icb6808edf96a17ec0b3073ba2486b3345a4a66ea Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/amd/cezanne/cpu.c M src/soc/amd/picasso/cpu.c M src/soc/amd/sabrina/cpu.c 3 files changed, 17 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/64867/1
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 818e4d8..0e4d7c6 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -35,21 +35,12 @@ x86_mtrr_check(); }
-static void post_mp_init(void) -{ - global_smi_enable(); - - /* SMMINFO only needs to be set up when booting from S5 */ - if (!acpi_is_wakeup_s3()) - apm_control(APM_CNT_SMMINFO); -} - static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .relocation_handler = smm_relocation_handler, - .post_mp_init = post_mp_init, + .post_mp_init = global_smi_enable, };
void mp_init_cpus(struct bus *cpu_bus) @@ -60,6 +51,10 @@
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* SMMINFO only needs to be set up when booting from S5 */ + if (!acpi_is_wakeup_s3()) + apm_control(APM_CNT_SMMINFO); }
static void zen_2_3_init(struct device *dev) diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index f14ee49..e0daa33 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -39,21 +39,12 @@ x86_mtrr_check(); }
-static void post_mp_init(void) -{ - global_smi_enable(); - - /* SMMINFO only needs to be set up when booting from S5 */ - if (!acpi_is_wakeup_s3()) - apm_control(APM_CNT_SMMINFO); -} - static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .relocation_handler = smm_relocation_handler, - .post_mp_init = post_mp_init, + .post_mp_init = global_smi_enable, };
void mp_init_cpus(struct bus *cpu_bus) @@ -64,6 +55,11 @@
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* SMMINFO only needs to be set up when booting from S5 */ + if (!acpi_is_wakeup_s3()) + apm_control(APM_CNT_SMMINFO); + }
static void model_17_init(struct device *dev) diff --git a/src/soc/amd/sabrina/cpu.c b/src/soc/amd/sabrina/cpu.c index 9893a8b..5d3539f 100644 --- a/src/soc/amd/sabrina/cpu.c +++ b/src/soc/amd/sabrina/cpu.c @@ -2,6 +2,7 @@
/* TODO: Check if this is still correct */
+#include <acpi/acpi.h> #include <amdblocks/cpu.h> #include <amdblocks/mca.h> #include <amdblocks/reset.h> @@ -37,21 +38,12 @@ x86_mtrr_check(); }
-static void post_mp_init(void) -{ - global_smi_enable(); - - /* SMMINFO only needs to be set up when booting from S5 */ - if (!acpi_is_wakeup_s3()) - apm_control(APM_CNT_SMMINFO); -} - static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .relocation_handler = smm_relocation_handler, - .post_mp_init = post_mp_init, + .post_mp_init = global_smi_enable, };
void mp_init_cpus(struct bus *cpu_bus) @@ -62,6 +54,10 @@
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* SMMINFO only needs to be set up when booting from S5 */ + if (!acpi_is_wakeup_s3()) + apm_control(APM_CNT_SMMINFO); }
static void zen_2_3_init(struct device *dev)