Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage

[Hung-Te Lin (Code Review)]

Attention is currently required from: Shelley Chen, Paul Menzel, Angel Pons, Yu-Ping Wu, Jianjun Wang.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 )

Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage
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Patch Set 9:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/62359/comment/b9997fa4_180a7f1b 
PS9, Line 14: 100ms
> Is there a way to ensure this minimum delay of 100ms is still met? coreboot could be too fast in som […]

Agree with Angel's concern. When will we do next init? In ramstage? Although the romstage is usually longer than 100ms, I wonder if we can create some timestamp, and verify that in next init, and to do extra delay if it hasn't meet 100ms.

File src/soc/mediatek/mt8195/bootblock.c:

https://review.coreboot.org/c/coreboot/+/62359/comment/8077e745_7996a4a6 
PS9, Line 18: 
            : 	if (CONFIG(PCI))
            : 		mtk_pcie_pre_init();
I wonder if we can move this to bootblock_mainboard_init