Change in coreboot[master]: soc/intel: drop unneeded ISST configuration code

[Michael Niewöhner (Code Review)]

Hello  Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46460

to look at the new patch set (#7).

Change subject: soc/intel: drop unneeded ISST configuration code
......................................................................

soc/intel: drop unneeded ISST configuration code

The code configuring ISST (Intel SpeedShift Technology) sets the ISST
capability bits in CPUID.06H:EAX. It does *not* activate HWP (Hardware
P-States), which shall be done by the OS only.

Since the capability is enabled by default (opt-out), there is nothing
to do for us in the enabled-case. Practically speaking, there is no
value at all in disabling the capability, since one can configure the
OS to not enable HWP if that is desired.

The two other bits for EPP and HWP interrupt that were set by the code
are not set anymore, too. It was tested, on three platforms so far
(CML-U, KBL-H, SKL-U), that these are set as well by default in the
MSRs reset value (0x1cc0).

To reduce complexity and duplicated code without actual benefit, this
code gets dropped. The remaining dt option will be dropped in CB:46462.

Test: Linux on Supermicro X11SSM-F detects and enables HWP:
[    0.415017] intel_pstate: HWP enabled

Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7
Signed-off-by: Michael Niewöhner 
---
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/elkhartlake/cpu.c
M src/soc/intel/icelake/cpu.c
M src/soc/intel/jasperlake/cpu.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/tigerlake/cpu.c
7 files changed, 0 insertions(+), 196 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46460/7