[S] Change in coreboot[master]: soc/amd/smm: Check the SMM TSEG size

[Himanshu Sahdev (Code Review)]

Attention is currently required from: Arthur Heymans, Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel, Zheng Bao.

Himanshu Sahdev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75405?usp=email )

Change subject: soc/amd/smm: Check the SMM TSEG size
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Patch Set 6: Code-Review+1

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/75405/comment/1443c3f1_115a49e5 :
PS3, Line 10: The SMM TSEG size should be less than SMM reserved size, bigger than
            : 8M, and power of 2.
> I can not find the solid proof that it should be power of 2.
> I checked the AGESA and platform code. They do use the value of power of 2 but don't say why.

https://edc.intel.com/content/www/us/en/design/publications/12th-generation-...
As per this intel datasheet:
```
NOTE: BIOS must program TSEGMB to a 8MB naturally aligned boundary.
```
^This seems the reason for the extra sanity check of 8 MB within ${src}/cpu/intel/model_2065x/model_2065x.h alike instances.

About power of 2:
Alignment of an address depends on the power of 2. An address is aligned to X(chosen power of 2) if its alignment is Xn+0.
Though a datum is naturally aligned if its address is aligned to its size.

(Please correct me if I am wrong)The reason here is the alignment!?