Attention is currently required from: Angel Pons.
Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34833 )
Change subject: nb/intel/gm45: Split DDR2 I/O init out ......................................................................
Patch Set 9:
(3 comments)
File src/northbridge/intel/gm45/raminit.c:
https://review.coreboot.org/c/coreboot/+/34833/comment/d698b649_91cc25f2 PS4, Line 1521:
Spurious extra line?
Not sure what you mean by this or if it is still relevant
https://review.coreboot.org/c/coreboot/+/34833/comment/12457a6d_7c3744d7 PS4, Line 1786: <<
Spacing?
Are you referring to the spacing around all of the shift operators? There's a lot of those without the spaces throughout the patchtrain
https://review.coreboot.org/c/coreboot/+/34833/comment/950cf112_02143d26 PS4, Line 1817: switch (ddr2clock) { : case MEM_CLOCK_667MT: : tmp |= (2 << 8) | 0xc; : break; : case MEM_CLOCK_800MT: : tmp |= (3 << 8) | 0xa; : break; : default: : die("Wrong clock"); : }
Maybe fuse this with the previous switch? the die() here will never be reached
Done
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Nicholas Chin (Code Review)