Change in coreboot[master]: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46261 )

Change subject: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
......................................................................

soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox

This SOC overrides the common PMC device and instantiates the
PMC device in the SSDT.  It needs to call the common PMC function
to provide the IPC mailbox method.

The common PCIe RTD3 driver can also be enabled which will allow
mainboards to enable Runtime D3 power control for PCIe devices.

BUG=b:160996445
TEST=boot on volteer with this driver enabled for the NVMe device
in the devicetree and disassemble the SSDT to ensure that the RTD3
code is present.

Signed-off-by: Duncan Laurie 
Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/pmc.c
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46261/1

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 4df2e85..0be2225 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -45,6 +45,7 @@
    select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
    select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
    select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
    select SOC_INTEL_COMMON_BLOCK_SA
    select SOC_INTEL_COMMON_BLOCK_SMM
    select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c
index f2f8a06..a7705de 100644
--- a/src/soc/intel/tigerlake/pmc.c
+++ b/src/soc/intel/tigerlake/pmc.c
@@ -119,6 +119,9 @@
    acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
    acpigen_write_resourcetemplate_footer();

+	/* Define IPC Write Method */
+	pmc_acpi_fill_ssdt_ipc_write_method();
+
    acpigen_pop_len(); /* PMC Device */
    acpigen_pop_len(); /* Scope */

[Duncan Laurie (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46261

to look at the new patch set (#4).

Change subject: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
......................................................................

soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox

This SOC overrides the common PMC device and instantiates the
PMC device in the SSDT.  It needs to call the common PMC function
to provide the IPC mailbox method.

The common PCIe RTD3 driver can also be enabled which will allow
mainboards to enable Runtime D3 power control for PCIe devices.

BUG=b:160996445
TEST=boot on volteer with this driver enabled for the NVMe device
in the devicetree and disassemble the SSDT to ensure that the RTD3
code is present.

Signed-off-by: Duncan Laurie 
Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/pmc.c
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46261/4

[Duncan Laurie (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46261

to look at the new patch set (#5).

Change subject: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
......................................................................

soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox

This SOC overrides the common PMC device and instantiates the PMC device
in the SSDT.  It needs to call the common PMC function to provide the
IPC mailbox method.

The common PCIe RTD3 driver can also be enabled which will allow
mainboards to enable Runtime D3 power control for PCIe devices.

BUG=b:160996445
TEST=boot on volteer with this driver enabled for the NVMe device in the
devicetree and disassemble the SSDT to ensure the RTD3 code is present.

Signed-off-by: Duncan Laurie 
Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/pmc.c
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46261/5

[Sukumar Ghorai (Code Review)]

Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46261 )

Change subject: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
......................................................................

Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46261/10/src/soc/intel/tigerlake/pm... 
File src/soc/intel/tigerlake/pmc.c:

https://review.coreboot.org/c/coreboot/+/46261/10/src/soc/intel/tigerlake/pm... 
PS10, Line 123: 	pmc_ipc_acpi_fill_ssdt();
#include <intelblocks/pmc_ipc.h> required

[Duncan Laurie (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46261

to look at the new patch set (#11).

Change subject: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
......................................................................

soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox

This SOC overrides the common PMC device and instantiates the PMC device
in the SSDT.  It needs to call the common PMC function to provide the
IPC mailbox method.

The common PCIe RTD3 driver can also be enabled which will allow
mainboards to enable Runtime D3 power control for PCIe devices.

BUG=b:160996445
TEST=boot on volteer with this driver enabled for the NVMe device in the
devicetree and disassemble the SSDT to ensure the RTD3 code is present.

Signed-off-by: Duncan Laurie 
Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/pmc.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46261/11

[Duncan Laurie (Code Review)]

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46261 )

Change subject: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
......................................................................

Patch Set 12:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46261/10/src/soc/intel/tigerlake/pm... 
File src/soc/intel/tigerlake/pmc.c:

https://review.coreboot.org/c/coreboot/+/46261/10/src/soc/intel/tigerlake/pm... 
PS10, Line 123: 	pmc_ipc_acpi_fill_ssdt();
> #include <intelblocks/pmc_ipc. […]

Done

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46261 )

Change subject: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
......................................................................

Patch Set 13: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46261 )

Change subject: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
......................................................................

Patch Set 15: Code-Review+2

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46261 )

Change subject: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
......................................................................

soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox

This SOC overrides the common PMC device and instantiates the PMC device
in the SSDT.  It needs to call the common PMC function to provide the
IPC mailbox method.

The common PCIe RTD3 driver can also be enabled which will allow
mainboards to enable Runtime D3 power control for PCIe devices.

BUG=b:160996445
TEST=boot on volteer with this driver enabled for the NVMe device in the
devicetree and disassemble the SSDT to ensure the RTD3 code is present.

Signed-off-by: Duncan Laurie 
Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46261
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/pmc.c
2 files changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 507f871..e117842 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -50,6 +50,7 @@
    select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
    select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
    select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
    select SOC_INTEL_COMMON_BLOCK_SA
    select SOC_INTEL_COMMON_BLOCK_SMM
    select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c
index dbf3671..c5a4ae5 100644
--- a/src/soc/intel/tigerlake/pmc.c
+++ b/src/soc/intel/tigerlake/pmc.c
@@ -13,6 +13,7 @@
 #include <drivers/intel/pmc_mux/chip.h>
 #include <intelblocks/pmc.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/pmc_ipc.h>
 #include <intelblocks/rtc.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
@@ -119,6 +120,10 @@
    acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
    acpigen_write_resourcetemplate_footer();

+	/* Define IPC Write Method */
+	if (CONFIG(PMC_IPC_ACPI_INTERFACE))
+		pmc_ipc_acpi_fill_ssdt();
+
    acpigen_pop_len(); /* PMC Device */
    acpigen_pop_len(); /* Scope */