Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39229 )
Change subject: mb/intel/tglrvp: pin mux for Display ports ......................................................................
mb/intel/tglrvp: pin mux for Display ports
Add addtional pin mux for eDP for DP portA and enable DP port1. These pin mux were done in FSPs, this pin mux is for bypassing pin mux in FSPs
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver.
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39229/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 8638b80..05fb9fef 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -54,7 +54,14 @@
/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { -/* ToDo: Fill early gpio configurations for TPM and WWAN */ + /* DP */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */ + PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */ + PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */ + PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */ + PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */ };
const struct pad_config *variant_gpio_table(size_t *num)
Wonkyu Kim has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/39229 )
Change subject: mb/intel/tglrvp: pin mux for Display ports ......................................................................
mb/intel/tglrvp: pin mux for Display ports
Add addtional pin mux for eDP for DP portA and enable DP port1. These pin mux were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver.
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39229/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39229
to look at the new patch set (#3).
Change subject: mb/intel/tglrvp: pin mux for Display ports ......................................................................
mb/intel/tglrvp: pin mux for Display ports
Add additional pin muxes for eDP for DP portA and enable DP port1. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver.
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39229/3
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39229 )
Change subject: mb/intel/tglrvp: pin mux for Display ports ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39229/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39229/3//COMMIT_MSG@7 PS3, Line 7: mb/intel/tglrvp: pin mux for Display ports
Add pin mux …
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39229
to look at the new patch set (#4).
Change subject: mb/intel/tglrvp: Add pin mux for Display ports ......................................................................
mb/intel/tglrvp: Add pin mux for Display ports
Add additional pin muxes for eDP for DP portA and enable DP port1. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver.
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39229/4
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39229 )
Change subject: mb/intel/tglrvp: Add pin mux for Display ports ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/39229/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39229/3//COMMIT_MSG@7 PS3, Line 7: mb/intel/tglrvp: pin mux for Display ports
Add pin mux …
Ack
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39229
to look at the new patch set (#5).
Change subject: mb/intel/tglrvp: Add pin mux for Display ports ......................................................................
mb/intel/tglrvp: Add pin mux for Display ports
Add additional pin muxes for eDP for DP portA and enable DP port1. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver.
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 2 files changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39229/5
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39229
to look at the new patch set (#6).
Change subject: mb/intel/tglrvp: Update Display ports for RVP ......................................................................
mb/intel/tglrvp: Update Display ports for RVP
Enable DdiPortBHpd and additional pin muxes for DPs. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver.
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 2 files changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39229/6
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39229
to look at the new patch set (#7).
Change subject: mb/intel/tglrvp: Update display ports for RVP ......................................................................
mb/intel/tglrvp: Update display ports for RVP
Enable DdiPortBHpd and additional pin muxes for DPs. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver.
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 2 files changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39229/7
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39229
to look at the new patch set (#8).
Change subject: mb/intel/tglrvp: Update display ports for RVP ......................................................................
mb/intel/tglrvp: Update display ports for RVP
Enable DdiPortBHpd and additional pin muxes for DPs. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver.
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 2 files changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39229/8
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39229 )
Change subject: mb/intel/tglrvp: Update display ports for RVP ......................................................................
Patch Set 8: Code-Review+1
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39229 )
Change subject: mb/intel/tglrvp: Update display ports for RVP ......................................................................
Patch Set 8: Code-Review+2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39229 )
Change subject: mb/intel/tglrvp: Update display ports for RVP ......................................................................
Patch Set 8: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39229 )
Change subject: mb/intel/tglrvp: Update display ports for RVP ......................................................................
mb/intel/tglrvp: Update display ports for RVP
Enable DdiPortBHpd and additional pin muxes for DPs. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver.
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39229 Reviewed-by: Shaunak Saha shaunak.saha@intel.com Reviewed-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 2 files changed, 10 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Shaunak Saha: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index e61690e..5888db0 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -52,6 +52,7 @@ # enabling EDP in PortA register "DdiPortAConfig" = "1"
+ register "DdiPortBHpd" = "1" register "DdiPort1Hpd" = "1" register "DdiPort1Ddc" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 46ed5a2..073926a 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -61,7 +61,6 @@
/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /*Audio */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ @@ -83,6 +82,15 @@ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */
+ /* DP */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */ + PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */ + PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */ + PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */ + PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */ + PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */ };
const struct pad_config *variant_gpio_table(size_t *num)