Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37829 )
Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ......................................................................
asus/am1i-a: Switch away from ROMCC_BOOTBLOCK
Switching was done by moving a SIO configuration and a clocks setup from 'romstage.c' to 'bootblock.c', following the example of change CB:37719 (fc749b2).
TEST=Boots into Artix Linux 2019 without a problem.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I780fa87cb9cb3c45844c388331ef89eb8eb70ebb --- M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/am1i-a/Kconfig.name M src/mainboard/asus/am1i-a/Makefile.inc R src/mainboard/asus/am1i-a/bootblock.c 4 files changed, 13 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/37829/1
diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index 8ccb174..947c2c5 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -1,12 +1,8 @@ -config BOARD_ASUS_AM1I_A - def_bool n - if BOARD_ASUS_AM1I_A
config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/asus/am1i-a/Kconfig.name b/src/mainboard/asus/am1i-a/Kconfig.name index 57c6227..55b4a3c 100644 --- a/src/mainboard/asus/am1i-a/Kconfig.name +++ b/src/mainboard/asus/am1i-a/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_ASUS_AM1I_A -# bool"AM1I-A" +config BOARD_ASUS_AM1I_A + bool"AM1I-A" diff --git a/src/mainboard/asus/am1i-a/Makefile.inc b/src/mainboard/asus/am1i-a/Makefile.inc index f8895fa..4dde2cf 100644 --- a/src/mainboard/asus/am1i-a/Makefile.inc +++ b/src/mainboard/asus/am1i-a/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. #
+bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/bootblock.c similarity index 83% rename from src/mainboard/asus/am1i-a/romstage.c rename to src/mainboard/asus/am1i-a/bootblock.c index de85325..07e3945 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/bootblock.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Sergej Ivanov getinaks@gmail.com - * Copyright (C) 2018 Gergely Kiss mail.gery@gmail.com - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,12 +11,9 @@ * GNU General Public License for more details. */
-#include <arch/io.h> +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> #include <device/pnp_ops.h> -#include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/common/amd_defs.h> -#include <southbridge/amd/agesa/hudson/hudson.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8623e/it8623e.h>
@@ -118,33 +111,22 @@ ite_reg_write(dev, 0xfb, 0x00); }
-void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - int i; - u32 val; - u8 byte; - pci_devfn_t dev; - u32 *addr32; + volatile u32 i, val, *addr32;
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. * Otherwise the serial output is bad code. */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); + pm_write8(0xd2, 0x0);
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xEA, 0xcd6); - outb(0x1, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev2, 0x44, 0xff03ffd5); + pm_write8(0xea, 0x1);
/* Enable the AcpiMmio space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); + pm_write8(0x24, 0x1);
/* Configure ClkDrvStr1 settings */ addr32 = (u32 *)0xfed80e24; @@ -154,15 +136,11 @@ addr32 = (u32 *)0xfed80e40; *addr32 = 0x000c4050;
- /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f & 4e, 4f */ - pci_write_config8(dev, 0x48, byte); - + /* Configure SIO as made under vendor BIOS */ ite_gpio_conf(GPIO_DEV); ite_evc_conf(ENVC_DEV);
+ /* Enable serial output on it8623e */ ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_kill_watchdog(GPIO_DEV);
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37829 )
Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/K... File src/mainboard/asus/am1i-a/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/K... PS1, Line 2: bool"AM1I-A" bool "AM1I-A"
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37829 )
Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 1:
(4 comments)
Thanks!
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... File src/mainboard/asus/am1i-a/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... PS1, Line 123: pm_write8(0xd2, 0x0); already in hudson/bootblock.c
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... PS1, Line 125: /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ Can you check datasheet if this is valid for fam16kb.
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... PS1, Line 129: pm_write8(0x24, 0x1); already in hudson/bootblock.c
BTW: pm_write8 only works with AcpiMmio enabled
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... PS1, Line 150: * because of the buffer ICS551M If we believe the comments we do not need this.
For "Larne" which I believe is codename for some CRB, super-io might be add-on debug device carrying LPC signals on a cable. Not sure. Marshall?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37829 )
Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37829/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37829/1//COMMIT_MSG@10 PS1, Line 10: a clocks setup the clock setup
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37829 )
Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 1:
(1 comment)
By the way, it was surprisingly easy to switch away from ROMCC_BOOTBLOCK, and booted fine at the first attempt! I wonder if this approach could be done for the other AMD boards even without testing (if no one could test at the moment).
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... File src/mainboard/asus/am1i-a/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... PS1, Line 125: /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
Can you check datasheet if this is valid for fam16kb.
I checked https://www.amd.com/system/files/TechDocs/48751_16h_bkdg.pdf page 859 - and there is no 0xEA, only 0xE8 and 0xEB; either this is undocumented or no such a register. Also I couldn't find another PM register providing this functionality, and to be honest - don't know where this code came from (it has been there since the initial commit), why it's disabling this PCI bridge or why GPIO32/33 could be needed for other uses. A bit later I could try building without it.
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37829 )
Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 1:
Marshall, if you could, please answer our question about that Larne code in the end of bootblock.c - https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b...
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37829 )
Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 1:
Yes, I did advertise this as an easy task on the list, after Michal and I completed the first boards for each fam. Mike, you know now what is redundant and what to clean up, go and do the reviews on Elyes work that fixes many of the remaining AGESA boards.
I still see little value dragging along boards without test results but I do not deny you from the chance of +2 reviews on those.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37829 )
Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 1: Code-Review+1
Hello HAOUAS Elyes, Marshall Dawson, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37829
to look at the new patch set (#2).
Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ......................................................................
asus/am1i-a: Switch away from ROMCC_BOOTBLOCK
Switching was done by moving a SIO configuration and the clocks setup from 'romstage.c' to 'bootblock.c', following the example of change CB:37719 (fc749b2).
TEST=Boots into Artix Linux 2019 without a problem.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I780fa87cb9cb3c45844c388331ef89eb8eb70ebb --- M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/am1i-a/Kconfig.name M src/mainboard/asus/am1i-a/Makefile.inc R src/mainboard/asus/am1i-a/bootblock.c 4 files changed, 11 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/37829/2
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37829 )
Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 2:
(6 comments)
MSI MS7721 is at CB:37737 (merged), Jetway nf81-t56n-lf is at CB:37750. So I'll do it for Gizmo2 CB:37869 and Biostar A68N-5200 CB:37872 - perhaps the last widely available consumer boards from your at-danger-of-removal list ( https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/VUGRM... ). I don't care much for the expensive&rare AMD CRBs, only for these people's boards.
https://review.coreboot.org/c/coreboot/+/37829/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37829/1//COMMIT_MSG@10 PS1, Line 10: a clocks setup
the clock setup
Done.
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/K... File src/mainboard/asus/am1i-a/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/K... PS1, Line 2: bool"AM1I-A"
bool "AM1I-A"
Done.
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... File src/mainboard/asus/am1i-a/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... PS1, Line 123: pm_write8(0xd2, 0x0);
already in hudson/bootblock. […]
Removed.
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... PS1, Line 125: /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
I checked https://www.amd.com/system/files/TechDocs/48751_16h_bkdg. […]
Didn't remove yet, need more info.
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... PS1, Line 129: pm_write8(0x24, 0x1);
already in hudson/bootblock.c […]
Removed.
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... PS1, Line 150: * because of the buffer ICS551M
If we believe the comments we do not need this. […]
Didn't remove yet, need more info.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37829 )
Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... File src/mainboard/asus/am1i-a/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... PS1, Line 125: /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
Didn't remove yet, need more info.
Ack
https://review.coreboot.org/c/coreboot/+/37829/1/src/mainboard/asus/am1i-a/b... PS1, Line 150: * because of the buffer ICS551M
Didn't remove yet, need more info.
Ack
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37829 )
Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 2: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37829 )
Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ......................................................................
asus/am1i-a: Switch away from ROMCC_BOOTBLOCK
Switching was done by moving a SIO configuration and the clocks setup from 'romstage.c' to 'bootblock.c', following the example of change CB:37719 (fc749b2).
TEST=Boots into Artix Linux 2019 without a problem.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I780fa87cb9cb3c45844c388331ef89eb8eb70ebb Reviewed-on: https://review.coreboot.org/c/coreboot/+/37829 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/am1i-a/Kconfig.name M src/mainboard/asus/am1i-a/Makefile.inc R src/mainboard/asus/am1i-a/bootblock.c 4 files changed, 11 insertions(+), 45 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index 8ccb174..947c2c5 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -1,12 +1,8 @@ -config BOARD_ASUS_AM1I_A - def_bool n - if BOARD_ASUS_AM1I_A
config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/asus/am1i-a/Kconfig.name b/src/mainboard/asus/am1i-a/Kconfig.name index 57c6227..840e821 100644 --- a/src/mainboard/asus/am1i-a/Kconfig.name +++ b/src/mainboard/asus/am1i-a/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_ASUS_AM1I_A -# bool"AM1I-A" +config BOARD_ASUS_AM1I_A + bool "AM1I-A" diff --git a/src/mainboard/asus/am1i-a/Makefile.inc b/src/mainboard/asus/am1i-a/Makefile.inc index f8895fa..4dde2cf 100644 --- a/src/mainboard/asus/am1i-a/Makefile.inc +++ b/src/mainboard/asus/am1i-a/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. #
+bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/bootblock.c similarity index 78% rename from src/mainboard/asus/am1i-a/romstage.c rename to src/mainboard/asus/am1i-a/bootblock.c index de85325..d4017cf 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/bootblock.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Sergej Ivanov getinaks@gmail.com - * Copyright (C) 2018 Gergely Kiss mail.gery@gmail.com - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,12 +11,9 @@ * GNU General Public License for more details. */
-#include <arch/io.h> +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> #include <device/pnp_ops.h> -#include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/common/amd_defs.h> -#include <southbridge/amd/agesa/hudson/hudson.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8623e/it8623e.h>
@@ -118,33 +111,12 @@ ite_reg_write(dev, 0xfb, 0x00); }
-void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - int i; - u32 val; - u8 byte; - pci_devfn_t dev; - u32 *addr32; - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); + volatile u32 i, val, *addr32;
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xEA, 0xcd6); - outb(0x1, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev2, 0x44, 0xff03ffd5); - - /* Enable the AcpiMmio space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); + pm_write8(0xea, 0x1);
/* Configure ClkDrvStr1 settings */ addr32 = (u32 *)0xfed80e24; @@ -154,15 +126,11 @@ addr32 = (u32 *)0xfed80e40; *addr32 = 0x000c4050;
- /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f & 4e, 4f */ - pci_write_config8(dev, 0x48, byte); - + /* Configure SIO as made under vendor BIOS */ ite_gpio_conf(GPIO_DEV); ite_evc_conf(ENVC_DEV);
+ /* Enable serial output on it8623e */ ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_kill_watchdog(GPIO_DEV);
-
HAOUAS Elyes (Code Review) -
Kyösti Mälkki (Code Review)
-
Mike Banon (Code Review)
-
Paul Menzel (Code Review)