Change in coreboot[master]: Revert "soc/intel/jasperlake: Publish single GPIO ACPI device"

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40434 )

Change subject: Revert "soc/intel/jasperlake: Publish single GPIO ACPI device"
......................................................................

Revert "soc/intel/jasperlake: Publish single GPIO ACPI device"

This reverts commit 30ab312322dba872917a96e82e269065c80556c7.

Kernel v5.4 has added implementation for jasperlake pin-ctrl driver.
GPIO community based ACPI device needs to be published for compliance.

Change-Id: If6ad0067c07a07aceed4b7b5492e4275074a3e2b
---
M src/soc/intel/jasperlake/acpi/gpio.asl
1 file changed, 79 insertions(+), 41 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40434/1

diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl
index f1e4498..2b4aff0 100644
--- a/src/soc/intel/jasperlake/acpi/gpio.asl
+++ b/src/soc/intel/jasperlake/acpi/gpio.asl
@@ -1,69 +1,107 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
-
-#include <intelblocks/gpio.h>
 #include <soc/gpio_defs.h>
 #include <soc/irq.h>
 #include <soc/pcr_ids.h>
+#include <intelblocks/gpio.h>
 #include "gpio_op.asl"

-Device (GPIO)
+Device (GCM0)
 {
    Name (_HID, CROS_GPIO_NAME)
    Name (_UID, 0)
-	Name (_DDN, "GPIO Controller")
+	Name (_DDN, "GPIO Controller Community 0")

Name (RBUF, ResourceTemplate()
    {
-		Memory32Fixed (ReadWrite, 0, 0, COM0)
-		Memory32Fixed (ReadWrite, 0, 0, COM1)
-		Memory32Fixed (ReadWrite, 0, 0, COM2)
-		Memory32Fixed (ReadWrite, 0, 0, COM4)
-		Memory32Fixed (ReadWrite, 0, 0, COM5)
+		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0)
    	Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
    		{ GPIO_IRQ14 }
    })
-
    Method (_CRS, 0, NotSerialized)
    {
-		/* GPIO Community 0 */
    	CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
-		CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
    	BAS0 = ^^PCRB (PID_GPIOCOM0)
-		LEN0 = GPIO_BASE_SIZE
-
-		/* GPIO Community 1 */
-		CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
-		CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
-		BAS1 = ^^PCRB (PID_GPIOCOM1)
-		LEN1 = GPIO_BASE_SIZE
-
-		/* GPIO Community 2 */
-		CreateDWordField (^RBUF, ^COM2._BAS, BAS2)
-		CreateDWordField (^RBUF, ^COM2._LEN, LEN2)
-		BAS2 = ^^PCRB (PID_GPIOCOM2)
-		LEN2 = GPIO_BASE_SIZE
-
-		/* GPIO Community 4 */
-		CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
-		CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
-		BAS4 = ^^PCRB (PID_GPIOCOM4)
-		LEN4 = GPIO_BASE_SIZE
-
-		/* GPIO Community 5 */
-		CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
-		CreateDWordField (^RBUF, ^COM5._LEN, LEN5)
-		BAS5 = ^^PCRB (PID_GPIOCOM5)
-		LEN5 = GPIO_BASE_SIZE
-
-		Return (RBUF)
+		Return (^RBUF)
    }
-
-	Method (_STA, 0, NotSerialized)
+	Method (_STA)
    {
    	Return (0xF)
    }
 }
+
+Device (GCM1)
+{
+	Name (_HID, CROS_GPIO_NAME)
+	Name (_UID, 1)
+	Name (_DDN, "GPIO Controller Community 1")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+			{ GPIO_IRQ14 }
+	})
+	Method (_CRS, 0, NotSerialized)
+	{
+		CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+		BAS1 = ^^PCRB (PID_GPIOCOM1)
+		Return (^RBUF)
+	}
+	Method (_STA)
+	{
+		Return (0xF)
+	}
+}
+
+Device (GCM4)
+{
+	Name (_HID, CROS_GPIO_NAME)
+	Name (_UID, 4)
+	Name (_DDN, "GPIO Controller Community 4")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+			{ GPIO_IRQ14 }
+	})
+	Method (_CRS, 0, NotSerialized)
+	{
+		CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+		BAS4 = ^^PCRB (PID_GPIOCOM4)
+		Return (^RBUF)
+	}
+	Method (_STA)
+	{
+		Return (0xF)
+	}
+}
+
+Device (GCM5)
+{
+	Name (_HID, CROS_GPIO_NAME)
+	Name (_UID, 5)
+	Name (_DDN, "GPIO Controller Community 5")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+		{ GPIO_IRQ14 }
+	})
+	Method (_CRS, 0, NotSerialized)
+	{
+		CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
+		BAS5 = ^^PCRB (PID_GPIOCOM5)
+		Return (^RBUF)
+	}
+	Method (_STA)
+	{
+		Return (0xF)
+	}
+}
+
 /*
  * Get GPIO DW0 Address
  * Arg0 - GPIO Number

[Aamir Bohra (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40434

to look at the new patch set (#2).

Change subject: Revert "soc/intel/jasperlake: Publish single GPIO ACPI device"
......................................................................

Revert "soc/intel/jasperlake: Publish single GPIO ACPI device"

This reverts commit 30ab312322dba872917a96e82e269065c80556c7.

Kernel v5.4 has added implementation for jasperlake pin-ctrl driver.
GPIO community based ACPI device needs to be published for compliance.

BUG=b:150154277
TEST=pending
Change-Id: If6ad0067c07a07aceed4b7b5492e4275074a3e2b
---
M src/soc/intel/jasperlake/acpi/gpio.asl
1 file changed, 79 insertions(+), 41 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40434/2