Change in coreboot[master]: soc/intel/common: Add HECI Reset flow in the CSE driver

[Ravindra (Code Review)]

Attention is currently required from: Sridhar Siricilla, Paul Menzel, Ravindra, Patrick Rudolph.
Ravindra has uploaded a new patch set (#4) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/55363 )

Change subject: soc/intel/common: Add HECI Reset flow in the CSE driver
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soc/intel/common: Add HECI Reset flow in the CSE driver

The patch adds HECI Reset flow in the CSE driver. This is required as part
of the HECI Interface initialization in order to put the host and CSE into
a known good state for communication. This change is required to send
HECI commands before DRAM Init.

TEST=Run 50 cold reset cycles on Brya

Signed-off-by: Sridhar Siricilla 
Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba
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M src/soc/intel/common/block/cse/cse.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55363/4