[XS] Change in coreboot[main]: soc/intel/alderlake: Use CSE sync in ramstage config

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85108?usp=email )

Change subject: soc/intel/alderlake: Use CSE sync in ramstage config
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soc/intel/alderlake: Use CSE sync in ramstage config

This patch updates the eSOL rendering logic to use the
SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option instead of
SOC_INTEL_CSE_LITE_SKU.

The SOC_INTEL_CSE_LITE_SKU config option was incorrectly used to
determine whether to render eSOL during ramstage.

The SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option specifically
indicates whether CSE synchronization is performed during ramstage,
making it a more appropriate choice for this purpose.

This change ensures that eSOL is rendered correctly during ramstage on
platforms that require CSE synchronization.

TEST=Able to render eSOL during ramstage for google/trulo.

Change-Id: I0dd335d5653d774bb5a2e6d7b65831bba080f272
Signed-off-by: Subrata Banik 
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/85108/1

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index fc9721c..c98ce10 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -439,7 +439,7 @@
     * packed as part of the CBFS then CSE sync will be triggered. CSE sync can take
     * < 1-minute hence, let's inform the end user with an on-screen text message.
     */
-	if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) {
+	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()) {
    	if (esol_required) {
    		name = "memory training and CSE update";
    	} else {