Change in coreboot[master]: mb/intel/tglrvp: Update tglrvp_up3 devicetree - coreboot-gerrit

25 Dec 2019

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37929 )
Change subject: mb/intel/tglrvp: Update tglrvp_up3 devicetree
......................................................................
mb/intel/tglrvp: Update tglrvp_up3 devicetree
Update Tigerlake RVP UP3 devicetree to reflect devices used by
tglrvp_up3.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com
Change-Id: Idd0d9efe0ab4e050d2160f7662e4dc40a002672f
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
1 file changed, 96 insertions(+), 276 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/37929/1

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 76ceb30..2a1c49c 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -4,37 +4,25 @@
    	device lapic 0 on end
    end
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route. i.e. If this route changes then the affected GPE
-	# offset bits also need to be changed.
-	register "gpe0_dw0" = "GPP_B"
-	register "gpe0_dw1" = "GPP_D"
-	register "gpe0_dw2" = "GPP_E"
-
    # FSP configuration
-	register "SaGv" = "SaGv_Enabled"
+	register "SaGv" = "SaGv_Disabled"
    register "SmbusEnable" = "1"
-	register "ScsEmmcHs400Enabled" = "1"
-	register "SdCardPowerEnableActiveHigh" = "1"
-	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"	# USB3/2 Type A port1
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 WWAN
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 Bluetooth
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"	# Type-C Port1
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"	# Type-C Port2
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"	# Type-C Port3
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC3)"	# Type-C Port4
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"	# USB3/2 Type A port2
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"	# USB2 Type A port1
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"	# USB2 Type A port2
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"		# M.2 Bluetooth
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"		# USB3/2 Type A port1
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"		# Type-C Port2
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"		# Type-C Port3
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC3)"		# Type-C Port4
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"		# USB3/2 Type A port2
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"		# USB2 Type A port3
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"		# USB2 Type A port4
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port1
    register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3 WLAN
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# UNUSED
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# UNUSED
-	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# UNUSED
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Not used
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"	# USB3/USB2 Flex Connector
# Enable Pch iSCLK
    register "pch_isclk" = "1"
@@ -45,79 +33,20 @@
    # EC memory map range is 0x900-0x9ff
    register "gen3_dec" = "0x00fc0901"
-	register "PchHdaDspEnable" = "1"
-	register "PchHdaAudioLinkHda" = "1"
+	register "PrmrrSize" = "0x10000000"
-	register "PcieRpEnable[0]" = "1"
-	register "PcieRpEnable[1]" = "0"
-	register "PcieRpEnable[2]" = "0"
-	register "PcieRpEnable[3]" = "0"
-	register "PcieRpEnable[4]" = "1"
-	register "PcieRpEnable[5]" = "0"
-	register "PcieRpEnable[6]" = "0"
-	register "PcieRpEnable[7]" = "0"
+	register "PcieRpEnable[2]" = "1"
+	register "PcieRpEnable[3]" = "1"
    register "PcieRpEnable[8]" = "1"
-	register "PcieRpEnable[9]" = "0"
-	register "PcieRpEnable[10]" = "0"
-	register "PcieRpEnable[11]" = "0"
-	register "PcieRpEnable[12]" = "0"
-	register "PcieRpEnable[13]" = "0"
-	register "PcieRpEnable[14]" = "0"
-	register "PcieRpEnable[15]" = "0"
+	register "PcieRpEnable[9]" = "1"
-	register "PcieClkSrcUsage[0]" = "2"
-	register "PcieClkSrcUsage[1]" = "8"
-	register "PcieClkSrcUsage[2]" = "0xC"
-	register "PcieClkSrcUsage[3]" = "0x70"
-	register "PcieClkSrcUsage[4]" = "4"
-	register "PcieClkSrcUsage[5]" = "0xE"
-	register "PcieClkSrcUsage[6]" = "0x80"
-	register "PcieClkSrcUsage[7]" = "0x80"
-	register "PcieClkSrcUsage[8]" = "0x80"
-	register "PcieClkSrcUsage[9]" = "0x80"
-	register "PcieClkSrcUsage[10]" = "0x80"
-	register "PcieClkSrcUsage[11]" = "0x80"
-	register "PcieClkSrcUsage[12]" = "0x80"
-	register "PcieClkSrcUsage[13]" = "0x80"
-	register "PcieClkSrcUsage[14]" = "0x80"
-	register "PcieClkSrcUsage[15]" = "0x80"
-
-	register "PcieClkSrcClkReq[0]" = "0"
    register "PcieClkSrcClkReq[1]" = "1"
    register "PcieClkSrcClkReq[2]" = "2"
    register "PcieClkSrcClkReq[3]" = "3"
-	register "PcieClkSrcClkReq[4]" = "4"
-	register "PcieClkSrcClkReq[5]" = "5"
-	register "PcieClkSrcClkReq[6]" = "6"
-	register "PcieClkSrcClkReq[7]" = "7"
-	register "PcieClkSrcClkReq[8]" = "8"
-	register "PcieClkSrcClkReq[9]" = "9"
-	register "PcieClkSrcClkReq[10]" = "10"
-	register "PcieClkSrcClkReq[11]" = "11"
-	register "PcieClkSrcClkReq[12]" = "12"
-	register "PcieClkSrcClkReq[13]" = "13"
-	register "PcieClkSrcClkReq[14]" = "14"
-	register "PcieClkSrcClkReq[15]" = "15"
-	register "SataEnable" = "1"
-	register "SataSalpSupport" = "1"
-	register "SataPortsEnable[0]" = "1"
-	register "SataPortsEnable[1]" = "1"
-	register "SataPortsEnable[2]" = "1"
-	register "SataPortsEnable[3]" = "1"
-	register "SataPortsEnable[4]" = "1"
-	register "SataPortsEnable[5]" = "1"
-	register "SataPortsEnable[6]" = "1"
-	register "SataPortsEnable[7]" = "1"
-
-	register "SataPortsDevSlp[0]" = "1"
-	register "SataPortsDevSlp[1]" = "1"
-	register "SataPortsDevSlp[2]" = "1"
-	register "SataPortsDevSlp[3]" = "1"
-	register "SataPortsDevSlp[4]" = "1"
-	register "SataPortsDevSlp[5]" = "1"
-	register "SataPortsDevSlp[6]" = "1"
-	register "SataPortsDevSlp[7]" = "1"
+	register "PcieClkSrcUsage[1]" = "0x2"
+	register "PcieClkSrcUsage[2]" = "0x3"
+	register "PcieClkSrcUsage[3]" = "0x8"
register "SerialIoI2cMode" = "{
    	[PchSerialIoIndexI2C0]  = PchSerialIoPci,
@@ -130,208 +59,99 @@
register "SerialIoGSpiMode" = "{
    	[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
-		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
    	[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
    }"
register "SerialIoGSpiCsMode" = "{
-		[PchSerialIoIndexGSPI0] = 1,
-		[PchSerialIoIndexGSPI1] = 1,
-		[PchSerialIoIndexGSPI2] = 1,
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI2] = 0,
+		[PchSerialIoIndexGSPI3] = 0,
    }"
register "SerialIoGSpiCsState" = "{
    	[PchSerialIoIndexGSPI0] = 0,
    	[PchSerialIoIndexGSPI1] = 0,
    	[PchSerialIoIndexGSPI2] = 0,
+		[PchSerialIoIndexGSPI3] = 0,
    }"
register "SerialIoUartMode" = "{
    	[PchSerialIoIndexUART0] = PchSerialIoDisabled,
    	[PchSerialIoIndexUART1] = PchSerialIoDisabled,
-		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
-	}"
-
-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
-	# Enable DPTF
-	register "dptf_enable" = "1"
-
-	# GPIO for SD card detect
-	register "sdcard_cd_gpio" = "GPP_G5"
-
-	# Enable S0ix
-	register "s0ix_enable" = "0"
-
-	register "common_soc_config" = "{
-		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
-		.gspi[1] = {
-			.speed_mhz = 1,
-			.early_init = 1,
-		},
+		[PchSerialIoIndexUART2] = PchSerialIoPci,
    }"
device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 04.0 off  end # SA Thermal device
-		device pci 12.0 off  end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 14.0 on
-			chip drivers/usb/acpi
-				register "desc" = ""Root Hub""
-				register "type" = "UPC_TYPE_HUB"
-				device usb 0.0 on
-					chip drivers/usb/acpi
-						register "desc" = ""USB3/2 Type-A Left Lower""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.0 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""WWAN""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.1 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""Bluetooth""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 2.2 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB C Connector 1""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.3 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB C Connector 2""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.4 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB C Connector 3""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.5 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB C Connector 4""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device usb 2.6 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3/2 Type-A Left Upper""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.7 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-A Right Lower""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.8 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB2 Type-A Right Upper""
-						register "type" = "UPC_TYPE_A"
-						device usb 2.9 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3/2 Type-A Left Lower""
-						register "type" = "UPC_TYPE_A"
-						device usb 3.0 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3/2 Type-A Left Upper""
-						register "type" = "UPC_TYPE_A"
-						device usb 3.1 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""WLAN""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.2 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3 Port Unused1""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.3 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3 Port Unused2""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.4 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB3 Port Unused3""
-						register "type" = "UPC_TYPE_INTERNAL"
-						device usb 3.5 on end
-					end
-				end
-			end
-		end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.2 off end # PMC SRAM
-		chip drivers/intel/wifi
-			register "wake" = "GPE0_PME_B0"
-			device pci 14.3 on  end # CNVi wifi
-		end
-		device pci 14.5 on  end # SDCard
-		device pci 15.0 on
-			chip drivers/i2c/hid
-				register "generic.hid" = ""ALPS0000""
-				register "generic.desc" = ""Touchpad""
-				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)"
-				register "hid_desc_reg_offset" = "0x20"
-				device i2c 2c on end
-			end
-		end # I2C 0
-		device pci 15.1 on end # I2C #1
-		device pci 15.2 on end # I2C #2
-		device pci 15.3 on end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 on  end # SATA
-		device pci 19.0 on  end # I2C #4
-		device pci 19.1 off end # I2C #5
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on
-			chip drivers/intel/wifi
-				register "wake" = "GPE0_PCI_EXP"
-				device pci 00.0 on end
-			end
-		end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1e.0 on  end # UART #0
-		device pci 1e.1 off end # UART #1
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 on
-			chip drivers/spi/acpi
-				register "hid" = "ACPI_DT_NAMESPACE_HID"
-				register "compat_string" = ""google,cr50""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
-				device spi 0 on end
-			end
-		end # GSPI #1
-		device pci 1f.0 on end # eSPI Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 off end # GbE
+		#From EDS(575683)
+		device pci 00.0 on  end # Host Bridge		0x9A14:U/0x9A12:Y
+		device pci 02.0 on  end # Graphics
+		device pci 04.0 on  end # DPTF			0x9A03
+		device pci 05.0 on  end # IPU			0x9A19
+		device pci 06.0 on  end # PEG60			0x9A09
+		device pci 07.0 off  end # TBT_PCIe0		0x9A23
+		device pci 07.1 off  end # TBT_PCIe1		0x9A25
+		device pci 07.2 off  end # TBT_PCIe2		0x9A27
+		device pci 07.3 off  end # TBT_PCIe3		0x9A29
+		device pci 08.0 off  end # GNA			0x9A11
+		device pci 09.0 off  end # NPK			0x9A33
+		device pci 0a.0 off  end # Crash-log SRAM	0x9A0D
+		device pci 0d.0 on  end # USB xHCI		0x9A13
+		device pci 0d.1 on  end # USB xDCI (OTG)	0x9A15
+		device pci 0d.2 off  end # TBT DMA0		0x9A1B
+		device pci 0d.3 off  end # TBT DMA1		0x9A1D
+		device pci 0e.0 on  end # VMD			0x9A0B
+
+		# From PCH EDS(576591)
+		device pci 10.2 off  end # CNVi: BT		0xA0F5 - A0F7
+		device pci 10.6 off  end # THC0			0xA0D0
+		device pci 10.7 off  end # THC1			0xA0D1
+		device pci 12.0 off  end # SensorHUB		0xA0FC
+		device pci 12.6 off  end # GSPI2		0x34FB
+		device pci 13.0 off  end # GSPI3		0xA0FD
+		device pci 14.0 on  end # USB3.1 xHCI 		0xA0ED
+		device pci 14.1 on  end # USB3.1 xDCI		0xA0EE
+		device pci 14.2 on  end # Shared RAM		0xA0EF
+		device pci 14.3 off  end # CNVi: WiFi		0xA0F0 - A0F3
+		device pci 15.0 on  end	# I2C0			0xA0E8
+		device pci 15.1 on  end # I2C1			0xA0E9
+		device pci 15.2 on  end # I2C2			0xA0EA
+		device pci 15.3 on  end # I2C3			0xA0EB
+		device pci 16.0 on  end # HECI1			0xA0E0
+		device pci 16.1 off  end # HECI2		0xA0E1
+		device pci 16.2 off  end # CSME			0xA0E2
+		device pci 16.3 off  end # CSME			0xA0E3
+		device pci 16.4 off  end # HECI3		0xA0E4
+		device pci 16.5 off  end # HECI4		0xA0E5
+		device pci 17.0 off  end # SATA			0xA0D3
+		device pci 19.0 off  end # I2C4			0xA0C5
+		device pci 19.1 on  end # I2C5			0xA0C6
+		device pci 19.2 on  end # UART2			0xA0C7
+		device pci 1c.0 off  end # RP1			0xA0B8
+		device pci 1c.1 off  end # RP2			0xA0B9
+		device pci 1c.2 on  end # RP3			0xA0BA
+		device pci 1c.3 on  end # RP4			0xA0BB
+		device pci 1c.4 off  end # RP5			0xA0BC
+		device pci 1c.5 off  end # RP6			0xA0BD
+		device pci 1c.6 off  end # RP7			0xA0BE
+		device pci 1c.7 off  end # RP8			0xA0BF
+		device pci 1d.0 on  end # RP9			0xA0B0
+		device pci 1d.1 off  end # RP10			0xA0B1
+		device pci 1d.2 on  end # RP11			0xA0B2
+		device pci 1d.3 off  end # RP12			0xA0B3
+		device pci 1e.0 off  end # UART0		0xA0A8
+		device pci 1e.1 off  end # UART1		0xA0A9
+		device pci 1e.2 off  end # GSPI0		0xA0AA
+		device pci 1e.3 off  end # GSPI1		0xA0AB
+		device pci 1f.0 on  end # eSPI			0xA080 - A09F
+		device pci 1f.1 on  end # P2SB			0xA0A0
+		device pci 1f.2 on  end # PMC			0xA0A1
+		device pci 1f.3 on  end # Intel HD audio	0xA0C8-A0CF
+		device pci 1f.4 on  end # SMBus			0xA0A3
+		device pci 1f.5 on  end # SPI			0xA0A4
+		device pci 1f.6 off  end # GbE			0x15E1/0x15E2
+		device pci 1f.7 off  end # TH			0xA0A6
    end
 end
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idd0d9efe0ab4e050d2160f7662e4dc40a002672f
Gerrit-Change-Number: 37929
Gerrit-PatchSet: 1
Gerrit-Owner: Ravishankar Sarawadi ravishankar.sarawadi@intel.com
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