Change in coreboot[master]: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 )
Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group ......................................................................
Patch Set 6:
(5 comments)
https://review.coreboot.org/c/coreboot/+/46842/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46842/6//COMMIT_MSG@27 PS6, Line 27: Correcting the sequence by moving some of the reserved gpio within : community (that's also same in pinctrl driver), helps with the issue. What you are really doing is creating pad groups as per the EDS. That is also what the linux kernel driver does.
https://review.coreboot.org/c/coreboot/+/46842/6/src/soc/intel/jasperlake/gp... File src/soc/intel/jasperlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/46842/6/src/soc/intel/jasperlake/gp... PS6, Line 36: 0 This is not correct. It should be 320: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/th...
https://review.coreboot.org/c/coreboot/+/46842/6/src/soc/intel/jasperlake/gp... PS6, Line 38: GPIO_RSVD_10 Not for this change, but I think this GPIO should be named as per EDS. The name is already being used in kernel, so I don't think there is any problem to update it in coreboot too.
https://review.coreboot.org/c/coreboot/+/46842/6/src/soc/intel/jasperlake/gp... PS6, Line 39: GPIO_RSVD_11 Same here and the other GPIO_RSVD* below.
https://review.coreboot.org/c/coreboot/+/46842/6/src/soc/intel/jasperlake/gp... PS6, Line 64: 320 This is 0 as per the above kernel link.
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Furquan Shaikh (Code Review)