Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55232 )
Change subject: [WIP] mb/dell: Add OptiPlex 7020 SFF port ......................................................................
[WIP] mb/dell: Add OptiPlex 7020 SFF port
Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Signed-off-by: Mate Kukri kukri.mate@gmail.com --- M Makefile.inc A src/mainboard/dell/optiplex_7020/Kconfig A src/mainboard/dell/optiplex_7020/Kconfig.name A src/mainboard/dell/optiplex_7020/Makefile.inc A src/mainboard/dell/optiplex_7020/acpi/ec.asl A src/mainboard/dell/optiplex_7020/acpi/platform.asl A src/mainboard/dell/optiplex_7020/acpi/superio.asl A src/mainboard/dell/optiplex_7020/board_info.txt A src/mainboard/dell/optiplex_7020/bootblock.c A src/mainboard/dell/optiplex_7020/cmos.default A src/mainboard/dell/optiplex_7020/cmos.layout A src/mainboard/dell/optiplex_7020/data.vbt A src/mainboard/dell/optiplex_7020/devicetree.cb A src/mainboard/dell/optiplex_7020/dsdt.asl A src/mainboard/dell/optiplex_7020/gma-mainboard.ads A src/mainboard/dell/optiplex_7020/gpio.c A src/mainboard/dell/optiplex_7020/hda_verb.c A src/mainboard/dell/optiplex_7020/io.h A src/mainboard/dell/optiplex_7020/mainboard.c A src/mainboard/dell/optiplex_7020/romstage.c A src/mainboard/dell/optiplex_7020/smscprog.c M src/northbridge/intel/haswell/raminit.c M src/southbridge/intel/lynxpoint/early_pch.c 23 files changed, 1,334 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/55232/1
diff --git a/Makefile.inc b/Makefile.inc index eb505e5..e1da353 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -488,7 +488,7 @@ endif
ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) -CFLAGS_common += -Werror +# CFLAGS_common += -Werror endif ifneq ($(GDB_DEBUG),) CFLAGS_common += -Og diff --git a/src/mainboard/dell/optiplex_7020/Kconfig b/src/mainboard/dell/optiplex_7020/Kconfig new file mode 100644 index 0000000..57ca13b --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/Kconfig @@ -0,0 +1,32 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_DELL_OPTIPLEX_7020 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_12288 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + +config CBFS_SIZE + hex + default 0x100000 + +config MAINBOARD_DIR + string + default "dell/optiplex_7020" + +config MAINBOARD_PART_NUMBER + string + default "OptiPlex 7020" + +endif diff --git a/src/mainboard/dell/optiplex_7020/Kconfig.name b/src/mainboard/dell/optiplex_7020/Kconfig.name new file mode 100644 index 0000000..73600a6 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_OPTIPLEX_7020 + bool "OptiPlex 7020" diff --git a/src/mainboard/dell/optiplex_7020/Makefile.inc b/src/mainboard/dell/optiplex_7020/Makefile.inc new file mode 100644 index 0000000..d5e44fb --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += bootblock.c smscprog.c diff --git a/src/mainboard/dell/optiplex_7020/acpi/ec.asl b/src/mainboard/dell/optiplex_7020/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/acpi/ec.asl diff --git a/src/mainboard/dell/optiplex_7020/acpi/platform.asl b/src/mainboard/dell/optiplex_7020/acpi/platform.asl new file mode 100644 index 0000000..7615a32 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/acpi/platform.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + +} + +Scope (_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 0xAA) + Name (_STA, 0x0B) + + Name (_PRW, Package() { 8, 3}) + } +} diff --git a/src/mainboard/dell/optiplex_7020/acpi/superio.asl b/src/mainboard/dell/optiplex_7020/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/acpi/superio.asl diff --git a/src/mainboard/dell/optiplex_7020/board_info.txt b/src/mainboard/dell/optiplex_7020/board_info.txt new file mode 100644 index 0000000..38d931f --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.dell.com/support/home/en-us/product-support/product/optiplex-702... +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/dell/optiplex_7020/bootblock.c b/src/mainboard/dell/optiplex_7020/bootblock.c new file mode 100644 index 0000000..02d2863 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/bootblock.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <console/console.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void smsc5555_setup(void); + +void mainboard_config_superio(void) +{ + smsc5555_setup(); +} diff --git a/src/mainboard/dell/optiplex_7020/cmos.default b/src/mainboard/dell/optiplex_7020/cmos.default new file mode 100644 index 0000000..c51001c --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Disable diff --git a/src/mainboard/dell/optiplex_7020/cmos.layout b/src/mainboard/dell/optiplex_7020/cmos.layout new file mode 100644 index 0000000..c9ba76c --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/cmos.layout @@ -0,0 +1,58 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 4 debug_level + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 5 power_on_after_fail + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/dell/optiplex_7020/data.vbt b/src/mainboard/dell/optiplex_7020/data.vbt new file mode 100644 index 0000000..1779f3b --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/data.vbt Binary files differ diff --git a/src/mainboard/dell/optiplex_7020/devicetree.cb b/src/mainboard/dell/optiplex_7020/devicetree.cb new file mode 100644 index 0000000..e057185 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/devicetree.cb @@ -0,0 +1,76 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + # This mainboard has VGA + register "gpu_ddi_e_connected" = "1" + + device cpu_cluster 0 on + chip cpu/intel/haswell + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x1028 0x05a5 + end + + device pci 01.0 off end # PCIe graphics + + device pci 02.0 on # VGA controller + subsystemid 0x1028 0x05a5 + end + + device pci 03.0 on # Mini-HD audio + subsystemid 0x1028 0x05a5 + end + + chip southbridge/intel/lynxpoint + register "sata_port_map" = "0x33" + + register "gen1_dec" = "0x00000295" # Super I/O HWM + + device pci 14.0 on # xHCI controller + subsystemid 0x1028 0x05a5 + end + device pci 16.0 on # Management Engine interface 1 + subsystemid 0x1028 0x05a5 + end + device pci 16.1 off end # Management Engine interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 on # Management Engine KT + subsystemid 0x1028 0x05a5 + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1028 0x05a4 + end + device pci 1a.0 on # EHCI controller #2 + subsystemid 0x1028 0x05a5 + end + device pci 1b.0 on # HD audio controller + subsystemid 0x1028 0x05a5 + end + device pci 1c.0 off end # PCIe port #1 + device pci 1c.1 off end # PCIe port #2 + device pci 1c.2 off end # PCIe port #3 + device pci 1c.3 off end # TODO: what's this? + device pci 1c.4 off end # TODO: what's this? + device pci 1c.5 off end # TODO: what's this? + device pci 1d.0 on # EHCI controller #1 + subsystemid 0x1028 0x05a5 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1028 0x05a5 + end + device pci 1f.2 on # SATA controller 1 + subsystemid 0x1028 0x05a5 + end + device pci 1f.3 on # SMBus + subsystemid 0x1028 0x05a5 + end + device pci 1f.5 off end # SATA controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/dell/optiplex_7020/dsdt.asl b/src/mainboard/dell/optiplex_7020/dsdt.asl new file mode 100644 index 0000000..8d4899a --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/dsdt.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20181031 /* OEM Revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) + { + Device (PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/dell/optiplex_7020/gma-mainboard.ads b/src/mainboard/dell/optiplex_7020/gma-mainboard.ads new file mode 100644 index 0000000..e7edb8e --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- TODO: Add DP ports to the list + ports : constant Port_List := + (Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/optiplex_7020/gpio.c b/src/mainboard/dell/optiplex_7020/gpio.c new file mode 100644 index 0000000..a281acf --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/gpio.c @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/optiplex_7020/hda_verb.c b/src/mainboard/dell/optiplex_7020/hda_verb.c new file mode 100644 index 0000000..467a888 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/hda_verb.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <stdint.h> +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0280, /* Realtek ALC3220 */ + 0x102805a5, /* Subsystem ID */ + 13, /* Number of entries */ + AZALIA_SUBVENDOR(1, 0x102805a5), + AZALIA_PIN_CFG(1, 0x12, 0x4008c000), + AZALIA_PIN_CFG(1, 0x13, 0x411111f0), + AZALIA_PIN_CFG(1, 0x14, 0x90170110), + AZALIA_PIN_CFG(1, 0x15, 0x0221401f), + AZALIA_PIN_CFG(1, 0x16, 0x411111f0), + AZALIA_PIN_CFG(1, 0x17, 0x411111f0), + AZALIA_PIN_CFG(1, 0x18, 0x01a13040), + AZALIA_PIN_CFG(1, 0x19, 0x411111f0), + AZALIA_PIN_CFG(1, 0x1a, 0x02a19030), + AZALIA_PIN_CFG(1, 0x1b, 0x01014020), + AZALIA_PIN_CFG(1, 0x1d, 0x40400001), + AZALIA_PIN_CFG(1, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/optiplex_7020/io.h b/src/mainboard/dell/optiplex_7020/io.h new file mode 100644 index 0000000..4dcaed0 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/io.h @@ -0,0 +1,87 @@ +// +// PCI, Port, and other I/O access helpers +// + +#ifndef IO_H +#define IO_H + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; + +static inline uint8_t inb(uint16_t port) +{ + uint8_t r; + asm volatile ("inb %1, %0" : "=a"(r) : "Nd"(port)); + return r; +} + +static inline uint16_t inw(uint16_t port) +{ + uint16_t r; + asm volatile ("inw %1, %0" : "=a"(r) : "Nd"(port)); + return r; +} + +static inline uint32_t inl(uint16_t port) +{ + uint32_t r; + asm volatile ("inl %1, %0" : "=a"(r) : "Nd"(port)); + return r; +} + +static inline void outb(uint8_t val, uint16_t port) +{ + asm volatile ("outb %0, %1" : : "a"(val), "Nd"(port)); +} + +static inline void outw(uint16_t val, uint16_t port) +{ + asm volatile ("outw %0, %1" : : "a"(val), "Nd"(port)); +} + +static inline void outl(uint32_t val, uint16_t port) +{ + asm volatile ("outl %0, %1" : : "a"(val), "Nd"(port)); +} + +#define PCI_ADDR(bus, dev, fun, offs) \ + (bus << 16 | dev << 11 | fun << 8 | offs) + +static inline uint32_t pci_read32(uint32_t addr) +{ + outl(0x80000000 | addr & 0xfffffffc, 0xcf8); + return inl(0xcfc); +} + +static inline uint16_t pci_read16(uint32_t addr) +{ + outl(0x80000000 | addr & 0xfffffffc, 0xcf8); + return inw(0xcfc + (addr & 2)); +} + +static inline uint8_t pci_read8(uint32_t addr) +{ + outl(0x80000000 | addr & 0xfffffffc, 0xcf8); + return inb(0xcfc + (addr & 3)); +} + +static inline void pci_write32(uint32_t addr, uint32_t val) +{ + outl(0x80000000 | addr & 0xfffffffc, 0xcf8); + outl(val, 0xcfc); +} + +static inline void pci_write16(uint32_t addr, uint16_t val) +{ + outl(0x80000000 | addr & 0xfffffffc, 0xcf8); + outw(val, 0xcfc + (addr & 2)); +} + +static inline void pci_write8(uint32_t addr, uint8_t val) +{ + outl(0x80000000 | addr & 0xfffffffc, 0xcf8); + outb(val, 0xcfc + (addr & 3)); +} + +#endif diff --git a/src/mainboard/dell/optiplex_7020/mainboard.c b/src/mainboard/dell/optiplex_7020/mainboard.c new file mode 100644 index 0000000..f0dbc3f --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/mainboard.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/dell/optiplex_7020/romstage.c b/src/mainboard/dell/optiplex_7020/romstage.c new file mode 100644 index 0000000..540a6a1 --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/romstage.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 0 }, + { 1, 0 }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, + { 0, USB_OC_PIN_SKIP }, +}; diff --git a/src/mainboard/dell/optiplex_7020/smscprog.c b/src/mainboard/dell/optiplex_7020/smscprog.c new file mode 100644 index 0000000..8527a3c --- /dev/null +++ b/src/mainboard/dell/optiplex_7020/smscprog.c @@ -0,0 +1,720 @@ +#include <console/console.h> +#include "io.h" + +// LPC registers +#define LPC_IO_DEC PCI_ADDR(0, 0x1f, 0, 0x80) +#define LPC_GEN1_DEC PCI_ADDR(0, 0x1f, 0, 0x84) +#define LPC_GEN2_DEC PCI_ADDR(0, 0x1f, 0, 0x88) +#define LPC_GEN3_DEC PCI_ADDR(0, 0x1f, 0, 0x8c) +#define LPC_GEN4_DEC PCI_ADDR(0, 0x1f, 0, 0x90) + +// I/O ports +#define SMSC_INDEX 0x2e +#define SMSC_DATA 0x2f + +// Global registers +#define GLO_LDN_SELECT 0x07 +#define GLO_DEVICE_ID 0x20 +#define GLO_DEVICE_REV 0x21 +#define GLO_DEVICE_MODE 0x24 + +// Activate the current LDN +#define GLO_LDN_ACTIVE 0x30 + +// UART registers +#define UART_CONFIG_SELECT 0xf0 + +// Runtime regsiters +#define RUNTIME_GPIO_SELECT 0x28 +#define RUNTIME_GPIO_READ 0x29 + +// +// Super I/O access +// + +static u8 smsc_read8(u8 offset) +{ + outb(offset, SMSC_INDEX); + return inb(SMSC_DATA); +} + +static u16 smsc_read16(u8 offset) +{ + u16 val = 0; + val |= smsc_read8(offset); + val |= smsc_read8(offset + 1) << 8; + return val; +} + +static u32 smsc_read32(u8 offset) +{ + u32 val = 0; + val |= smsc_read8(offset); + val |= smsc_read8(offset + 1) << 8; + val |= smsc_read8(offset + 2) << 16; + val |= smsc_read8(offset + 3) << 24; + return val; +} + +static void smsc_write8(u8 offset, u8 value) +{ + outb(offset, SMSC_INDEX); + outb(value, SMSC_DATA); +} + +static void smsc_write16(u8 offset, u16 value) +{ + smsc_write8(offset, value & 0xff); + smsc_write8(offset + 1, (value >> 8) & 0xff); +} + +static void smsc_write32(u8 offset, u32 value) +{ + smsc_write8(offset, value & 0xff); + smsc_write8(offset + 1, (value >> 8) & 0xff); + smsc_write8(offset + 2, (value >> 16) & 0xff); + smsc_write8(offset + 3, (value >> 24) & 0xff); +} + +// +// Super I/O registers +// + +enum smsc_width { + WIDTH8, + WIDTH16, + WIDTH32 +}; + +struct smsc_reg { + enum smsc_width width; + u8 offset; + const char *name; +}; + +struct smsc_ldn { + u8 ldn; + const char *name; + struct smsc_reg *regs; +}; + +static const struct smsc_ldn ALL_LDNS[] = { + { + .ldn = 0x3f, // NOTE: Selecting it is not necessary + .name = "Global Configuration ", + .regs = (const struct smsc_reg[]) { + { WIDTH8, 0x07, "Logical Device Number " }, + { WIDTH8, 0x20, "Device ID " }, + { WIDTH8, 0x21, "Device Revision " }, + { WIDTH8, 0x24, "Device Mode " }, + { 0, 0, 0 } + } + }, + { + .ldn = 0x0c, + .name = "LPC Interface ", + .regs = (const struct smsc_reg[]) { + { WIDTH8, 0x30, "Activate " }, + { WIDTH32, 0x60, "LPC Interface BAR " }, + { WIDTH32, 0x64, "EMI BAR " }, + { WIDTH32, 0x68, "UART1 BAR " }, + { WIDTH32, 0x6c, "UART2 BAR " }, + { WIDTH32, 0x70, "Runtime Registers BAR " }, + { WIDTH32, 0x74, "Undocumented BAR " }, + { WIDTH32, 0x78, "8042 BAR " }, + { WIDTH32, 0x7c, "Floppy Disk Controller BAR" }, + { WIDTH32, 0x80, "Parallel Port BAR " }, + { 0, 0, 0 } + } + }, + { + .ldn = 0x07, + .name = "UART1 ", + .regs = (const struct smsc_reg[]) { + { WIDTH8, 0x30, "Activate " }, + { WIDTH8, 0xf0, "Configuration Select " }, + { 0, 0, 0 } + } + }, + { 0, 0, 0 } +}; + + +// +// EMI access +// + +static u16 emi_iobase, runtime_iobase; + +static u8 emi_read8(u16 addr) +{ + outw(addr | 0x8000, emi_iobase + 2); + return inb(emi_iobase + 4); +} + +static u16 emi_read16(u16 addr) +{ + outw(addr | 0x8001, emi_iobase + 2); + return inw(emi_iobase + 4); +} + +static u32 emi_read32(u16 addr) +{ + outw(addr | 0x8002, emi_iobase + 2); + return inl(emi_iobase + 4); +} + +void emi_write8(u16 addr, u8 val) +{ + outw(addr | 0x8000, emi_iobase + 2); + outb(val, emi_iobase + 4); +} + +void emi_write16(u16 addr, u16 val) +{ + outw(addr | 0x8001, emi_iobase + 2); + outw(val, emi_iobase + 4); +} + +void emi_write32(u16 addr, u32 val) +{ + outw(addr | 0x8002, emi_iobase + 2); + outl(val, emi_iobase + 4); +} + +// +// Communicate with the EC (via EMI) +// + +void ec_initialize(void) +{ + inb(emi_iobase + 1); // EC-to-Host Mailbox + u8 int_src = inb(emi_iobase + 8) & 0xF6; // Interrupt Source (Byte 0) + outb(emi_iobase + 8, int_src); // Clear all Interrupts but 2, clear EC_WR +} + +_Bool ec_mailbox_xchg(u8 val) +{ + u8 int_src; + + outb(val, emi_iobase); // Send value via Host-to-EC mailbox + + do { + int_src = inb(emi_iobase + 8) & 0x71; // 0x71 = 0b1110001 + } while ( !int_src ); + outb(int_src, emi_iobase + 8); + + // Check EC_WR bit + if ((int_src & 1) == 0) + return 0; + + // Check if we got the same value via EC-to-Host mailbox + return val == inb(emi_iobase + 1); +} + +void ec_write(u8 addr1, u16 addr2, u8 val) +{ + u8 int_src = inb(emi_iobase + 0xA); // Save interrupt mask + outb(emi_iobase + 0xA, 0); // Mask all interrupts + emi_write16(0, (2 * addr1) | 0x101); + emi_write32(4, val | (addr2 << 16)); + ec_mailbox_xchg(1); + outb(emi_iobase + 0xA, int_src); // Restore interrupt mask +} + +u8 ec_read(u8 addr1, u16 addr2) +{ + u8 val = 0; + u8 int_src = inb(emi_iobase + 0xA); // save interrupt mask + outb(emi_iobase + 0xA, 0); // mask all interrupts + emi_write16(0, 2 * (addr1 | 0x80)); + emi_write32(4, addr2 << 16); + if (ec_mailbox_xchg(1)) + val = emi_read8(4); + outb(emi_iobase + 0xA, int_src); // restore interrupt mask + return val; +} + +// +// HWM initialization +// + +typedef struct { + u16 addr; + u8 val; +} BulkComEnt; + +static char *strcpy(char *s1, const char *s2) +{ + char *r = s1; + while (*s2) + *s1++ = *s2++; + return r; +} + +static void hwm_init(void) +{ + printk(BIOS_DEBUG, "EC 0xcb: %02x\n", ec_read(1, 0xcb)); + printk(BIOS_DEBUG, "EC 0xb8: %02x\n", ec_read(1, 0xb8)); + + BulkComEnt hwmInitSeq[75]; + + hwmInitSeq[0].addr = 0x2FC; + hwmInitSeq[1].addr = 0x2FD; + hwmInitSeq[2].addr = 5; + hwmInitSeq[3].addr = 0x19; + hwmInitSeq[4].addr = 0x1A; + hwmInitSeq[5].addr = 0x8A; + hwmInitSeq[6].addr = 0x8B; + hwmInitSeq[7].addr = 0x8C; + hwmInitSeq[8].addr = 0xBA; + hwmInitSeq[9].addr = 0xD1; + hwmInitSeq[10].addr = 0xD6; + hwmInitSeq[11].addr = 219; + hwmInitSeq[13].addr = 73; + hwmInitSeq[14].addr = 122; + hwmInitSeq[15].addr = 123; + hwmInitSeq[16].addr = 124; + hwmInitSeq[17].addr = 128; + hwmInitSeq[18].addr = 129; + hwmInitSeq[12].addr = 72; + hwmInitSeq[19].addr = 130; + hwmInitSeq[20].addr = 131; + hwmInitSeq[21].addr = 132; + hwmInitSeq[0].val = -96; + hwmInitSeq[1].val = 50; + hwmInitSeq[2].val = 119; + hwmInitSeq[3].val = 47; + hwmInitSeq[4].val = 47; + hwmInitSeq[5].val = 51; + hwmInitSeq[6].val = 51; + hwmInitSeq[7].val = 51; + hwmInitSeq[8].val = 16; + hwmInitSeq[9].val = -1; + hwmInitSeq[10].val = -1; + hwmInitSeq[11].val = -1; + hwmInitSeq[12].val = 0; + hwmInitSeq[13].val = 0; + hwmInitSeq[14].val = 0; + hwmInitSeq[15].val = 0; + hwmInitSeq[16].val = 0; + hwmInitSeq[17].val = 0; + hwmInitSeq[18].val = 0; + hwmInitSeq[19].val = 0; + hwmInitSeq[20].val = -69; + hwmInitSeq[21].val = -80; + hwmInitSeq[22].addr = 417; + hwmInitSeq[22].val = -120; + hwmInitSeq[23].addr = 420; + hwmInitSeq[24].addr = 136; + hwmInitSeq[25].addr = 137; + hwmInitSeq[26].addr = 160; + hwmInitSeq[27].addr = 161; + hwmInitSeq[28].addr = 162; + hwmInitSeq[29].addr = 164; + hwmInitSeq[30].addr = 165; + hwmInitSeq[31].addr = 166; + hwmInitSeq[32].addr = 171; + hwmInitSeq[33].addr = 173; + hwmInitSeq[34].addr = 183; + hwmInitSeq[35].addr = 98; + hwmInitSeq[42].addr = 89; + hwmInitSeq[43].addr = 97; + hwmInitSeq[44].addr = 444; + hwmInitSeq[45].addr = 445; + hwmInitSeq[23].val = 0x80; + hwmInitSeq[24].val = 0; + hwmInitSeq[25].val = 0; + hwmInitSeq[26].val = 2; + hwmInitSeq[27].val = 2; + hwmInitSeq[28].val = 2; + hwmInitSeq[29].val = 4; + hwmInitSeq[30].val = 4; + hwmInitSeq[31].val = 4; + hwmInitSeq[32].val = 0; + hwmInitSeq[33].val = 63; + hwmInitSeq[34].val = 7; + strcpy(&hwmInitSeq[35].val, "Pc"); + strcpy(&hwmInitSeq[36].val, "Fd"); + strcpy(&hwmInitSeq[37].val, "Pe"); + strcpy(&hwmInitSeq[38].val, "Ff"); + strcpy(&hwmInitSeq[39].val, "Pg"); + strcpy(&hwmInitSeq[40].val, "FW"); + hwmInitSeq[41].val = -104; + hwmInitSeq[42].val = -104; + hwmInitSeq[43].val = 124; + hwmInitSeq[44].val = 0; + hwmInitSeq[45].val = 0; + hwmInitSeq[46].addr = 443; + hwmInitSeq[46].val = 0; + hwmInitSeq[47].addr = 133; + hwmInitSeq[48].addr = 134; + hwmInitSeq[49].addr = 135; + hwmInitSeq[50].addr = 144; + hwmInitSeq[51].addr = 145; + hwmInitSeq[52].addr = 149; + hwmInitSeq[53].addr = 150; + hwmInitSeq[54].addr = 151; + hwmInitSeq[55].addr = 155; + hwmInitSeq[56].addr = 174; + hwmInitSeq[54].val = 0; + hwmInitSeq[55].val = 0; + hwmInitSeq[63].val = 0; + hwmInitSeq[57].addr = 175; + hwmInitSeq[58].addr = 179; + hwmInitSeq[64].addr = 691; + hwmInitSeq[59].addr = 196; + hwmInitSeq[65].addr = 692; + hwmInitSeq[66].addr = 716; + hwmInitSeq[67].addr = 720; + hwmInitSeq[68].addr = 722; + hwmInitSeq[59].val = -1; + hwmInitSeq[60].val = -1; + hwmInitSeq[61].val = -1; + hwmInitSeq[69].addr = 731; + hwmInitSeq[70].addr = 111; + hwmInitSeq[60].addr = 197; + hwmInitSeq[71].addr = 112; + hwmInitSeq[47].val = -35; + hwmInitSeq[48].val = -35; + hwmInitSeq[49].val = 7; + hwmInitSeq[50].val = -126; + hwmInitSeq[51].val = 94; + hwmInitSeq[52].val = 93; + hwmInitSeq[53].val = -87; + hwmInitSeq[56].val = -122; + hwmInitSeq[57].val = -122; + hwmInitSeq[58].val = 103; + hwmInitSeq[61].addr = 201; + hwmInitSeq[62].addr = 64; + hwmInitSeq[62].val = 1; + hwmInitSeq[63].addr = 0x2FC; + hwmInitSeq[64].val = -102; + hwmInitSeq[65].val = 5; + hwmInitSeq[66].val = 1; + hwmInitSeq[67].val = 76; + hwmInitSeq[68].val = 1; + hwmInitSeq[69].val = 1; + hwmInitSeq[70].val = 1; + hwmInitSeq[71].val = 2; + hwmInitSeq[72].addr = 113; + hwmInitSeq[72].val = 3; + hwmInitSeq[73].addr = 395; + hwmInitSeq[74].addr = 396; + hwmInitSeq[73].val = 3; + hwmInitSeq[74].val = 3; + + for (int i = 0; i < 75; ++i) { + ec_write(1, hwmInitSeq[i].addr, hwmInitSeq[i].val); + } +} + +// +// Super I/O initialization sequence +// + +struct sio_init { + u16 port; + u8 mask; + u8 val; +}; + +static void sio_init(void) +{ + static const struct sio_init init_table[] = { + { 0x2E, 0x0FF, 0x55 }, + { 0x2E, 0x0FF, 7 }, + { 0x2F, 0x0FF, 0x3F }, + { 0x2E, 0x0FF, 0x24 }, + { 0x2F, 0x0FB, 4 }, + { 0x2E, 0x0FF, 7 }, + { 0x2F, 0x0FF, 0x0C }, + { 0x2E, 0x0FF, 0x64 }, + { 0x2F, 0x0FF, 0x0F }, + { 0x2E, 0x0FF, 0x65 }, + { 0x2F, 0x0FF, 0x80 }, + { 0x2E, 0x0FF, 0x66 }, + { 0x2F, 0x0FF, 0 }, + { 0x2E, 0x0FF, 0x67 }, + { 0x2F, 0x0FF, 0x0A }, + { 0x2E, 0x0FF, 7 }, + { 0x2F, 0x0FF, 0x0C }, + { 0x2E, 0x0FF, 0x79 }, + { 0x2F, 0x0FF, 0x81 }, + { 0x2E, 0x0FF, 0x7A }, + { 0x2F, 0x0FF, 0x60 }, + { 0x2E, 0x0FF, 0x7B }, + { 0x2F, 0x0FF, 0 }, + { 0x2E, 0x0FF, 0x41 }, + { 0x2F, 0x0FF, 1 }, + { 0x2E, 0x0FF, 0x4C }, + { 0x2F, 0x0FF, 0x81 }, + { 0x2E, 0x0FF, 7 }, + { 0x2F, 0x0FF, 1 }, + { 0x2E, 0x0FF, 0x30 }, + { 0x2F, 0x0FF, 1 }, + { 0x2E, 0x0FF, 7 }, + { 0x2F, 0x0FF, 1 }, + { 0x2E, 0x0FF, 0x0F0 }, + { 0x2F, 0x0FF, 0 }, + { 0x2E, 0x0FF, 7 }, + { 0x2F, 0x0FF, 0x0C }, + { 0x2E, 0x0FF, 0x70 }, + { 0x2F, 0x0FF, 0x3F }, + { 0x2E, 0x0FF, 0x71 }, + { 0x2F, 0x0FF, 0x8A }, + { 0x2E, 0x0FF, 0x72 }, + { 0x2F, 0x0FF, 0x40 }, + { 0x2E, 0x0FF, 0x73 }, + { 0x2F, 0x0FF, 0x0A }, + { 0x0A40, 0x0FF, 1 }, + { 0x0A41, 0x0FF, 0 }, + { 0x0A45, 0x0FF, 0x18 }, + { 0x0A75, 0x0FF, 1 }, + { 0x0A65, 0x0FF, 0x0F }, + { 0x2E, 0x0FF, 0x0AA }, + }; + + for (int i = 0; i < ARRAY_SIZE(init_table); ++i) { + if (init_table[i].mask == 0xff) { + outb(init_table[i].val, init_table[i].port); + } else { + u8 prev = inb(init_table[i].port); + outb(prev & init_table[i].mask | init_table[i].val, + init_table[i].port); + } + } +} + + +int emi_data_rw(u16 addr, u8 *val, u8 flags) +{ + u8 ecmsg = inb(0xA01u); // Clear EC-to-Host mailbox + outb(ecmsg, 0xA01u); + + outb(0, 0xA02u); // Set EC address + outb(0x80u, 0xA03u); + + outb(flags, 0xA04u); + outb(1u, 0xA05u); + + outb(4u, 0xA02u); + + if ( (flags & 1) != 0 ) + outb(*val, 0xA04u); + outb(addr & 0xff, 0xA06u); + outb((addr >> 8) & 0xff, 0xA07u); + + + outb(1u, 0xA00u); + int timeout = 0; + do + ++timeout; + while ( (inb(0xA01u) & 1) == 0 && timeout < 0xFFF ); + + outb(0x31u, 0xA08u); + outb(0xC0u, 0xA00u); + + if ( (flags & 1) == 0 ) + *val = inb(0xA04u); + + return 0; +} + +struct emi_init { + u16 addr; + u8 val; + u8 pad; +}; + +static void emi_init(void) +{ + static const struct emi_init init_table1[] = { + { 0x8CC, 0x11, 0 }, + { 0x8D0, 0x11, 0 }, + { 0x88C, 0x10, 0 }, + { 0x890, 0x10, 0 }, + { 0x894, 0x10, 0 }, + { 0x898, 0x12, 0 }, + { 0x89C, 0x12, 0 }, + { 0x8A0, 0x10, 0 }, + { 0x8A4, 0x12, 0 }, + { 0x8A8, 0x10, 0 }, + { 0x820, 0x12, 0 }, + { 0x824, 0x12, 0 }, + { 0x878, 0x12, 0 }, + { 0x880, 0x12, 0 }, + { 0x884, 0x12, 0 }, + { 0x8E0, 0x12, 0 }, + { 0x8E4, 0x12, 0 }, + { 0x83C, 0x10, 0 }, + { 0x840, 0x10, 0 }, + { 0x844, 0x10, 0 }, + { 0x848, 0x10, 0 }, + { 0x84C, 0x10, 0 }, + { 0x850, 0x10, 0 }, + { 0x814, 0x11, 0 }, + }; + + for (int i = 0; i < ARRAY_SIZE(init_table1); ++i) { + emi_data_rw(init_table1[i].addr, &init_table1[i].val, 5); + } + + static const struct emi_init init_table2[] = { + { 5, 0x33, 0 }, + { 0x18, 0x2F, 0 }, + { 0x19, 0x2F, 0 }, + { 0x1A, 0x2F, 0 }, + { 0x83, 0x0BB, 0 }, + { 0x85, 0x0D9, 0 }, + { 0x86, 0x2C, 0 }, + { 0x8A, 0x34, 0 }, + { 0x8B, 0x60, 0 }, + { 0x90, 0x5E, 0 }, + { 0x91, 0x5E, 0 }, + { 0x92, 0x86, 0 }, + { 0x96, 0x0A4, 0 }, + { 0x97, 0x0A4, 0 }, + { 0x98, 0x0A4, 0 }, + { 0x9B, 0x0A4, 0 }, + { 0x0A0, 0x0A, 0 }, + { 0x0A1, 0x0A, 0 }, + { 0x0AE, 0x7C, 0 }, + { 0x0AF, 0x7C, 0 }, + { 0x0B0, 0x9E, 0 }, + { 0x0B3, 0x7C, 0 }, + { 0x0B6, 8, 0 }, + { 0x0B7, 8, 0 }, + { 0x0EA, 0x64, 0 }, + { 0x0EF, 0x0FF, 0 }, + { 0x0F8, 0x15, 0 }, + { 0x0F9, 0, 0 }, + { 0x0F0, 0x30, 0 }, + { 0x0FD, 1, 0 }, + { 0x1A1, 0, 0 }, + { 0x1A2, 0, 0 }, + { 0x1B1, 8, 0 }, + { 0x1BE, 0x90, 0 }, + { 0x280, 0x24, 0 }, + { 0x281, 0x13, 0 }, + { 0x282, 3, 0 }, + { 0x283, 0x0A, 0 }, + { 0x284, 0x80, 0 }, + { 0x285, 3, 0 }, + { 0x288, 0x80, 0 }, + { 0x289, 0x0C, 0 }, + { 0x28A, 3, 0 }, + { 0x28B, 0x0A, 0 }, + { 0x28C, 0x80, 0 }, + { 0x28D, 3, 0 }, + { 0x40, 1, 0 }, + }; + + for (int i = 0; i < ARRAY_SIZE(init_table2); ++i) { + emi_data_rw(init_table2[i].addr, &init_table2[i].val, 3); + } +} + +static void do_bios_init() +{ + // Change LPC config + pci_write16(LPC_IO_DEC, 0x0000); + pci_write32(LPC_GEN1_DEC, 0x007c0a01); + pci_write32(LPC_GEN2_DEC, 0x007c0901); + pci_write32(LPC_GEN3_DEC, 0x003c07e1); + pci_write32(LPC_GEN4_DEC, 0x001c0901); + + // Dump LPC config + printk(BIOS_DEBUG, "LPC_IO_DEC : %04x\n", pci_read16(LPC_IO_DEC)); + printk(BIOS_DEBUG, "LPC_GEN1_DEC: %08x\n", pci_read32(LPC_GEN1_DEC)); + printk(BIOS_DEBUG, "LPC_GEN2_DEC: %08x\n", pci_read32(LPC_GEN2_DEC)); + printk(BIOS_DEBUG, "LPC_GEN3_DEC: %08x\n", pci_read32(LPC_GEN3_DEC)); + printk(BIOS_DEBUG, "LPC_GEN4_DEC: %08x\n", pci_read32(LPC_GEN4_DEC)); + printk(BIOS_DEBUG, "\n"); + + // Do Sio and EMI Initialization + sio_init(); + printk(BIOS_DEBUG, "SIO init done!\n"); + emi_init(); + printk(BIOS_DEBUG, "EMI init done!\n"); +} + +void smsc5555_setup(void) +{ + do_bios_init(); + + // Save BAR values + outb(0x55, SMSC_INDEX); + smsc_write8(GLO_LDN_SELECT, 0x0c); + emi_iobase = smsc_read16(0x64 + 2); + runtime_iobase = smsc_read16(0x70 + 2); + + // Configure serial port + smsc_write16(0x68, 0x8707); + smsc_write16(0x68 + 2, CONFIG_TTYS0_BASE); // Serial Port I/O address + smsc_write8(GLO_LDN_SELECT, 0x07); + smsc_write8(GLO_LDN_ACTIVE, 0x01); + smsc_write8(UART_CONFIG_SELECT, 0x02); + + outb(0xaa, SMSC_INDEX); + + // Change LED to always on + outb(runtime_iobase + 0x25, 3); + // Setup EMI module + ec_initialize(); + // Do HWM init + hwm_init(); + + // Dump registers + outb(0x55, SMSC_INDEX); + for (struct smsc_ldn *ldn = ALL_LDNS; ldn->name != NULL; ++ldn) { + printk(BIOS_DEBUG, "Registers for %s (LDN: %02x)\n", ldn->name, ldn->ldn); + smsc_write8(GLO_LDN_SELECT, ldn->ldn); + for (struct smsc_reg *reg = ldn->regs; reg->name != NULL; ++reg) { + switch (reg->width) { + case WIDTH8: + printk(BIOS_DEBUG, " %s: %02x\n", reg->name, smsc_read8(reg->offset)); + break; + case WIDTH16: + printk(BIOS_DEBUG, " %s: %04x\n", reg->name, smsc_read16(reg->offset)); + break; + case WIDTH32: + printk(BIOS_DEBUG, " %s: %08x\n", reg->name, smsc_read32(reg->offset)); + break; + } + } + } + outb(0xaa, SMSC_INDEX); + +/* + // Dump EC Bank 0 + printk(BIOS_DEBUG, "\nEMI RAM Bank 0:\n"); + outw(0x0003, emi_iobase + 2); + for (int i = 0; i < 8192;) { + u32 val = inl(emi_iobase + 4); + printk(BIOS_DEBUG, "%08x ", val); + if ((i += 4) % 16 == 0) + printk(BIOS_DEBUG, "\n"); + } + + // Dump EC Bank 1o + printk(BIOS_DEBUG, "\nEMI RAM Bank 1:\n"); + outw(0x8003, emi_iobase + 2); + for (int i = 0; i < 8192;) { + u32 val = inl(emi_iobase + 4); + printk(BIOS_DEBUG, "%08x ", val); + if ((i += 4) % 16 == 0) + printk(BIOS_DEBUG, "\n"); + } + + + // Dump GPIOs + printk(BIOS_DEBUG, "\nGPIO:\n"); + for (int i = 0; i < 64;) { + outb(i, runtime_iobase + RUNTIME_GPIO_SELECT); + printk(BIOS_DEBUG, "%02x ", inb(runtime_iobase + RUNTIME_GPIO_READ)); + if (++i % 16 == 0) + printk(BIOS_DEBUG, "\n"); + } +*/ +} diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 9660961..9ee1023 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -139,7 +139,9 @@ */ entry = cbfs_ro_map("mrc.bin", NULL); if (entry) { + printk(BIOS_DEBUG, "Just before MRC entry!\n"); int rv = entry(pei_data); + printk(BIOS_DEBUG, "MRC entry returned: %d!\n", rv);
/* The mrc.bin reconfigures USB, so usbdebug needs to be reinitialized */ if (CONFIG(USBDEBUG_IN_PRE_RAM)) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 03823ff..c93f968 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -56,8 +56,8 @@
void pch_enable_lpc(void) { - const struct device *dev = pcidev_on_root(0x1f, 0); - const struct southbridge_intel_lynxpoint_config *config = NULL; + // const struct device *dev = pcidev_on_root(0x1f, 0); + // const struct southbridge_intel_lynxpoint_config *config = NULL;
/* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); @@ -67,18 +67,22 @@ COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config);
- /* Set up generic decode ranges */ - if (!dev) - return; - if (dev->chip_info) - config = dev->chip_info; - if (!config) - return; + // FIXME: this is a horible hack + // Decode EMI at 0xa00 + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0a01);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); + /* Set up generic decode ranges */ + // if (!dev) + // return; + // if (dev->chip_info) + // config = dev->chip_info; + // if (!config) + // return; + + // pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + // pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + // pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + // pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); }
void __weak mainboard_config_superio(void)
-
Máté Kukri (Code Review)