Change in coreboot[master]: sc7180: QSIP SPI NOR addressing mode

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mturney mturney (Code Review)

23 Jan 2020 23 Jan '20

4:57 p.m.

Hello Sajida Bhanu,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/38542

to review the following change.

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

sc7180: QSIP SPI NOR addressing mode

Putting SPI NOR 3 byte addressing mode as it is not supporting 4 byte addressing mode.

Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Signed-off-by: Veerabhadrarao Badiganti vbadigan@codeaurora.org Signed-off-by: Shaik Sajida Bhanu sbhanu@codeaurora.org --- M src/drivers/spi/spi_flash.c M src/drivers/spi/winbond.c 2 files changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38542/1

diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 90dd587..85cc160 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -459,6 +459,7 @@ { struct spi_slave spi; int ret = -1; + u8 reg8;

if (spi_setup_slave(bus, cs, &spi)) { printk(BIOS_WARNING, "SF: Failed to set up slave\n"); @@ -491,6 +492,21 @@ " CONFIG_ROM_SIZE 0x%x!!\n", flash->size, CONFIG_ROM_SIZE); } + + /*Check addressing mode*/ + spi_flash_cmd(&flash->spi, 0x15, &reg8, sizeof(reg8)); + + if (reg8 & 0x1 ) { + printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Falling back to 3 byte addressing mode\n", reg8); + } + + spi_flash_cmd(&flash->spi, 0xe9, NULL, 0); + spi_flash_cmd(&flash->spi, 0x15, &reg8, sizeof(reg8)); + if (reg8 & 0x1 ) { + printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Exiting 4 byte mode not working . Looping here\n ", reg8); + while(1); + } + return 0; }

diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index e85f59d..c4dc3d4 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -174,6 +174,14 @@ .bp_bits = 3, }, { + .id = 0x6019, + .name = "W25Q64DW", + .nr_sectors_shift = 11, + .fast_read_dual_output_support = 1, + .protection_granularity_shift = 17, + .bp_bits = 3, + }, + { .id = 0x4018, .name = "W25Q128_V", .nr_sectors_shift = 12,

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build bot (Jenkins) (Code Review)

23 Jan 23 Jan

5:04 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 1:

(7 comments)

https://review.coreboot.org/c/coreboot/+/38542/1/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/1/src/drivers/spi/spi_flash.c... PS1, Line 499: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/1/src/drivers/spi/spi_flash.c... PS1, Line 499: if (reg8 & 0x1 ) { braces {} are not necessary for single statement blocks

https://review.coreboot.org/c/coreboot/+/38542/1/src/drivers/spi/spi_flash.c... PS1, Line 500: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Falling back to 3 byte addressing mode\n", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/1/src/drivers/spi/spi_flash.c... PS1, Line 505: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/1/src/drivers/spi/spi_flash.c... PS1, Line 506: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Exiting 4 byte mode not working . Looping here\n ", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/1/src/drivers/spi/spi_flash.c... PS1, Line 507: while(1); space required before the open parenthesis '('

https://review.coreboot.org/c/coreboot/+/38542/1/src/drivers/spi/spi_flash.c... PS1, Line 507: while(1); trailing statements should be on next line

Aaron Durbin (Code Review)

5:14 p.m.

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38542/1/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/1/src/drivers/spi/spi_flash.c... PS1, Line 497: 0x15 Why are we issuing commands to devices that may not apply? This does not seem appropriate since you don't know what type of device is actually there. These commands are device specific. Likewise, this seems like a workaround for the part being potentially in a 4 byte addressing mode. However, I don't think this check belongs in the main part of the code here as well as being done unconditionally.

build bot (Jenkins) (Code Review)

24 Jan 24 Jan

5:57 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 2:

(7 comments)

https://review.coreboot.org/c/coreboot/+/38542/2/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/2/src/drivers/spi/spi_flash.c... PS2, Line 499: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/2/src/drivers/spi/spi_flash.c... PS2, Line 499: if (reg8 & 0x1 ) { braces {} are not necessary for single statement blocks

https://review.coreboot.org/c/coreboot/+/38542/2/src/drivers/spi/spi_flash.c... PS2, Line 500: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Falling back to 3 byte addressing mode\n", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/2/src/drivers/spi/spi_flash.c... PS2, Line 505: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/2/src/drivers/spi/spi_flash.c... PS2, Line 506: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Exiting 4 byte mode not working . Looping here\n ", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/2/src/drivers/spi/spi_flash.c... PS2, Line 507: while(1); space required before the open parenthesis '('

https://review.coreboot.org/c/coreboot/+/38542/2/src/drivers/spi/spi_flash.c... PS2, Line 507: while(1); trailing statements should be on next line

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 2 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-Comment-Date: Fri, 24 Jan 2020 16:57:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

build bot (Jenkins) (Code Review)

11:07 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 3:

(7 comments)

https://review.coreboot.org/c/coreboot/+/38542/3/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/3/src/drivers/spi/spi_flash.c... PS3, Line 499: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/3/src/drivers/spi/spi_flash.c... PS3, Line 499: if (reg8 & 0x1 ) { braces {} are not necessary for single statement blocks

https://review.coreboot.org/c/coreboot/+/38542/3/src/drivers/spi/spi_flash.c... PS3, Line 500: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Falling back to 3 byte addressing mode\n", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/3/src/drivers/spi/spi_flash.c... PS3, Line 505: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/3/src/drivers/spi/spi_flash.c... PS3, Line 506: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Exiting 4 byte mode not working . Looping here\n ", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/3/src/drivers/spi/spi_flash.c... PS3, Line 507: while(1); space required before the open parenthesis '('

https://review.coreboot.org/c/coreboot/+/38542/3/src/drivers/spi/spi_flash.c... PS3, Line 507: while(1); trailing statements should be on next line

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 3 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-Comment-Date: Fri, 24 Jan 2020 22:07:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

build bot (Jenkins) (Code Review)

11:59 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 4:

(7 comments)

https://review.coreboot.org/c/coreboot/+/38542/4/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/4/src/drivers/spi/spi_flash.c... PS4, Line 499: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/4/src/drivers/spi/spi_flash.c... PS4, Line 499: if (reg8 & 0x1 ) { braces {} are not necessary for single statement blocks

https://review.coreboot.org/c/coreboot/+/38542/4/src/drivers/spi/spi_flash.c... PS4, Line 500: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Falling back to 3 byte addressing mode\n", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/4/src/drivers/spi/spi_flash.c... PS4, Line 505: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/4/src/drivers/spi/spi_flash.c... PS4, Line 506: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Exiting 4 byte mode not working . Looping here\n ", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/4/src/drivers/spi/spi_flash.c... PS4, Line 507: while(1); space required before the open parenthesis '('

https://review.coreboot.org/c/coreboot/+/38542/4/src/drivers/spi/spi_flash.c... PS4, Line 507: while(1); trailing statements should be on next line

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 4 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-Comment-Date: Fri, 24 Jan 2020 22:59:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Julius Werner (Code Review)

25 Jan 25 Jan

2:57 a.m.

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 4:

Is this just a temporary patch you want to carry locally to enable your development board? If so, please prefix the subject with HACK: so people know that you're not intending it for merge and it doesn't need to be reviewed.

If you do want to merge this permanently, we can do that too but like Aaron said it needs to be done cleaner than this (would probably want to actually implement 4-byte address support then, rather than just disable it and have half the flash inaccessible). But considering that we're not planning to officially add your development board to coreboot and Trogdor isn't using this chip, I don't think we'll need to go there?

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 4 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-Comment-Date: Sat, 25 Jan 2020 01:57:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

build bot (Jenkins) (Code Review)

27 Jan 27 Jan

9:02 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 5:

(7 comments)

https://review.coreboot.org/c/coreboot/+/38542/5/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/5/src/drivers/spi/spi_flash.c... PS5, Line 499: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/5/src/drivers/spi/spi_flash.c... PS5, Line 499: if (reg8 & 0x1 ) { braces {} are not necessary for single statement blocks

https://review.coreboot.org/c/coreboot/+/38542/5/src/drivers/spi/spi_flash.c... PS5, Line 500: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Falling back to 3 byte addressing mode\n", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/5/src/drivers/spi/spi_flash.c... PS5, Line 505: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/5/src/drivers/spi/spi_flash.c... PS5, Line 506: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Exiting 4 byte mode not working . Looping here\n ", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/5/src/drivers/spi/spi_flash.c... PS5, Line 507: while(1); space required before the open parenthesis '('

https://review.coreboot.org/c/coreboot/+/38542/5/src/drivers/spi/spi_flash.c... PS5, Line 507: while(1); trailing statements should be on next line

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 5 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-Comment-Date: Mon, 27 Jan 2020 20:02:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Julius Werner (Code Review)

28 Jan 28 Jan

1:30 a.m.

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38542/5//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38542/5//COMMIT_MSG@7 PS5, Line 7: sc7180: QSIP SPI NOR addressing mode Please see my earlier comment and mark this HACK: (or let us know what you're planning to do with this patch).

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 5 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-Comment-Date: Tue, 28 Jan 2020 00:30:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Paul Menzel (Code Review)

4:10 p.m.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38542/5//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38542/5//COMMIT_MSG@9 PS5, Line 9: Putting SPI NOR 3 byte addressing mode as it is not supporting 4 byte addressing mode. The text width limit is 75 characters.

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 5 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Tue, 28 Jan 2020 15:10:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

build bot (Jenkins) (Code Review)

30 Jan 30 Jan

4:12 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 6:

(7 comments)

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c... PS6, Line 499: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c... PS6, Line 499: if (reg8 & 0x1 ) { braces {} are not necessary for single statement blocks

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c... PS6, Line 500: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Falling back to 3 byte addressing mode\n", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c... PS6, Line 505: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c... PS6, Line 506: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Exiting 4 byte mode not working . Looping here\n ", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c... PS6, Line 507: while(1); space required before the open parenthesis '('

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c... PS6, Line 507: while(1); trailing statements should be on next line

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 6 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Thu, 30 Jan 2020 15:12:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Ravi kumar (Code Review)

3 Feb 3 Feb

5:24 p.m.

Ravi kumar has uploaded a new patch set (#7) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

sc7180: QSIP SPI NOR addressing mode

Putting SPI NOR 3 byte addressing mode as it is not supporting 4 byte addressing mode.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38542/7

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 7 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

build bot (Jenkins) (Code Review)

5:26 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 7:

(7 comments)

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c... PS7, Line 504: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c... PS7, Line 504: if (reg8 & 0x1 ) { braces {} are not necessary for single statement blocks

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c... PS7, Line 505: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Falling back to 3 byte addressing mode\n", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c... PS7, Line 510: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c... PS7, Line 511: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Exiting 4 byte mode not working . Looping here\n ", reg8); line over 96 characters

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c... PS7, Line 512: while(1); space required before the open parenthesis '('

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c... PS7, Line 512: while(1); trailing statements should be on next line

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 7 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Mon, 03 Feb 2020 16:26:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

build bot (Jenkins) (Code Review)

5 Feb 5 Feb

2:21 a.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 8:

(9 comments)

https://review.coreboot.org/c/coreboot/+/38542/8/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/8/src/drivers/spi/spi_flash.c... PS8, Line 504: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/8/src/drivers/spi/spi_flash.c... PS8, Line 504: if (reg8 & 0x1 ) { braces {} are not necessary for single statement blocks

https://review.coreboot.org/c/coreboot/+/38542/8/src/drivers/spi/spi_flash.c... PS8, Line 505: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Falling back to 3 byte addressing mode\n", reg8); 'adressing' may be misspelled - perhaps 'addressing'?

https://review.coreboot.org/c/coreboot/+/38542/8/src/drivers/spi/spi_flash.c... PS8, Line 510: if (reg8 & 0x1 ) { space prohibited before that close parenthesis ')'

https://review.coreboot.org/c/coreboot/+/38542/8/src/drivers/spi/spi_flash.c... PS8, Line 511: printk(BIOS_WARNING, "4 byte adressing mode set:%02x\n. Exiting 4 byte mode not working . Looping here\n ", reg8); 'adressing' may be misspelled - perhaps 'addressing'?

https://review.coreboot.org/c/coreboot/+/38542/8/src/drivers/spi/spi_flash.c... PS8, Line 512: while(1); space required before the open parenthesis '('

https://review.coreboot.org/c/coreboot/+/38542/8/src/drivers/spi/spi_flash.c... PS8, Line 512: while(1); trailing statements should be on next line

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 8 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 05 Feb 2020 01:21:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

mturney mturney (Code Review)

10:23 p.m.

Hello Ravi kumar, build bot (Jenkins), Sajida Bhanu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38542

to look at the new patch set (#9).

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

sc7180: QSIP SPI NOR addressing mode

Force SPI NOR 3 byte addr mode as 4 byte addr mode is not supported.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38542/9

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 9 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

build bot (Jenkins) (Code Review)

10:26 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 9:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38542/9/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/9/src/drivers/spi/spi_flash.c... PS9, Line 515: while(1) space required before the open parenthesis '('

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 9 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 05 Feb 2020 21:26:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

build bot (Jenkins) (Code Review)

10:53 p.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38542/10/src/drivers/spi/spi_flash.... File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/10/src/drivers/spi/spi_flash.... PS10, Line 515: while(1) space required before the open parenthesis '('

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 10 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 05 Feb 2020 21:53:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

mturney mturney (Code Review)

7 Feb 7 Feb

7:47 p.m.

Hello Ravi kumar, build bot (Jenkins), Sajida Bhanu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38542

to look at the new patch set (#11).

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

sc7180: QSIP SPI NOR addressing mode

Force SPI NOR 3 byte addr mode as 4 byte addr mode is not supported.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38542/11

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 11 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Sajida Bhanu (Code Review)

14 Feb 14 Feb

12:56 p.m.

Sajida Bhanu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 12:

(7 comments)

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c... PS6, Line 499: if (reg8 & 0x1 ) {

...

braces {} are not necessary for single statement blocks

Done

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c... PS6, Line 499: if (reg8 & 0x1 ) {

...

space prohibited before that close parenthesis ')'

Done

...

line over 96 characters

sure

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c... PS6, Line 505: if (reg8 & 0x1 ) {

...

space prohibited before that close parenthesis ')'

Done

...

line over 96 characters

sure

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c... PS6, Line 507: while(1);

...

space required before the open parenthesis '('

Done

https://review.coreboot.org/c/coreboot/+/38542/6/src/drivers/spi/spi_flash.c... PS6, Line 507: while(1);

...

trailing statements should be on next line

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 12 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 14 Feb 2020 11:56:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: comment

Sajida Bhanu (Code Review)

12:57 p.m.

Sajida Bhanu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 12:

(7 comments)

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c... PS7, Line 504: if (reg8 & 0x1 ) {

...

space prohibited before that close parenthesis ')'

Done

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c... PS7, Line 504: if (reg8 & 0x1 ) {

...

braces {} are not necessary for single statement blocks

Done

...

line over 96 characters

sure

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c... PS7, Line 510: if (reg8 & 0x1 ) {

...

space prohibited before that close parenthesis ')'

done

...

line over 96 characters

sure

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c... PS7, Line 512: while(1);

...

trailing statements should be on next line

Done

https://review.coreboot.org/c/coreboot/+/38542/7/src/drivers/spi/spi_flash.c... PS7, Line 512: while(1);

...

space required before the open parenthesis '('

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 12 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 14 Feb 2020 11:57:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: comment

Sajida Bhanu (Code Review)

12:58 p.m.

Sajida Bhanu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 12:

(1 comment)

...

Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38542/10/src/drivers/spi/spi_flash.... File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/10/src/drivers/spi/spi_flash.... PS10, Line 515: while(1)

...

space required before the open parenthesis '('

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 12 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 14 Feb 2020 11:58:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: comment

Julius Werner (Code Review)

15 Feb 15 Feb

12:29 a.m.

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

Patch Set 12:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38542/10/src/drivers/spi/spi_flash.... File src/drivers/spi/spi_flash.c:

https://review.coreboot.org/c/coreboot/+/38542/10/src/drivers/spi/spi_flash.... PS10, Line 515: while(1)

...

Done

Hi Sajida,

Please read and reply to the comments from Aaron and me early in this patch thread. For now I am not expecting that we'll want to land this patch, so you don't need to spend time cleaning up linter warnings. If you do want to permanently land this patch, we'll need to discuss a different and more complicated approach to do that cleanly in a way that fits in our framework.

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 12 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 14 Feb 2020 23:29:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sajida Bhanu sbhanu@codeaurora.org Comment-In-Reply-To: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: comment

Ravi kumar (Code Review)

8:39 a.m.

Ravi kumar has uploaded a new patch set (#14) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

sc7180: QSIP SPI NOR addressing mode

Force SPI NOR 3 byte addr mode as 4 byte addr mode is not supported.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38542/14

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 14 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Ravi kumar (Code Review)

3 Mar 3 Mar

11:29 a.m.

Ravi kumar has uploaded a new patch set (#18) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: sc7180: QSIP SPI NOR addressing mode ......................................................................

sc7180: QSIP SPI NOR addressing mode

Force SPI NOR 3 byte addr mode as 4 byte addr mode is not supported.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38542/18

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 18 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

mturney mturney (Code Review)

6 Mar 6 Mar

10:21 p.m.

New subject: Change in coreboot[master]: HACK sc7180: QSIP SPI NOR addressing mode HACK

Hello Ravi kumar, build bot (Jenkins), Sajida Bhanu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38542

to look at the new patch set (#19).

Change subject: HACK sc7180: QSIP SPI NOR addressing mode HACK ......................................................................

HACK sc7180: QSIP SPI NOR addressing mode HACK

Force SPI NOR 3 byte addr mode as 4 byte addr mode is not supported.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38542/19

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 19 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Ravi kumar (Code Review)

8 May 8 May

2:40 p.m.

New subject: Change in coreboot[master]: HACK sc7180: QSIP SPI NOR addressing mode HACK

Ravi kumar has uploaded a new patch set (#27) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: HACK sc7180: QSIP SPI NOR addressing mode HACK ......................................................................

HACK sc7180: QSIP SPI NOR addressing mode HACK

Force SPI NOR 3 byte addr mode as 4 byte addr mode is not supported.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38542/27

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 27 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

mturney mturney (Code Review)

9 May 9 May

2:36 a.m.

New subject: Change in coreboot[master]: HACK sc7180: QSIP SPI NOR addressing mode HACK

Hello Ravi kumar, build bot (Jenkins), Sajida Bhanu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38542

to look at the new patch set (#28).

Change subject: HACK sc7180: QSIP SPI NOR addressing mode HACK ......................................................................

HACK sc7180: QSIP SPI NOR addressing mode HACK

Force SPI NOR 3 byte addr mode as 4 byte addr mode is not supported.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38542/28

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 28 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Ravi kumar (Code Review)

15 May 15 May

8:34 p.m.

New subject: Change in coreboot[master]: HACK sc7180: QSIP SPI NOR addressing mode HACK

Ravi kumar has uploaded a new patch set (#32) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: HACK sc7180: QSIP SPI NOR addressing mode HACK ......................................................................

HACK sc7180: QSIP SPI NOR addressing mode HACK

Force SPI NOR 3 byte addr mode as 4 byte addr mode is not supported.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38542/32

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 32 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Ravi kumar (Code Review)

10 Jun 10 Jun

7:19 p.m.

New subject: Change in coreboot[master]: HACK sc7180: QSIP SPI NOR addressing mode HACK

Ravi kumar has uploaded a new patch set (#39) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/38542 )

Change subject: HACK sc7180: QSIP SPI NOR addressing mode HACK ......................................................................

HACK sc7180: QSIP SPI NOR addressing mode HACK

Force SPI NOR 3 byte addr mode as 4 byte addr mode is not supported.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38542/39

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 39 Gerrit-Owner: mturney mturney mturney@codeaurora.org Gerrit-Reviewer: Ravi kumar rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu sbhanu@codeaurora.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Martin L Roth (Code Review)

7 Aug 7 Aug

10:18 p.m.

New subject: [S] Change in coreboot[master]: HACK sc7180: QSIP SPI NOR addressing mode HACK

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38542?usp=email )

Change subject: HACK sc7180: QSIP SPI NOR addressing mode HACK ......................................................................

Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.

-- To view, visit https://review.coreboot.org/c/coreboot/+/38542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232dde9387f0c83dd1578f3cbab4ab85a711349d Gerrit-Change-Number: 38542 Gerrit-PatchSet: 44 Gerrit-Owner: mturney mturney quic_mturney@quicinc.com Gerrit-Reviewer: Ravi Kumar Bokka rbokka@codeaurora.org Gerrit-Reviewer: Sajida Bhanu quic_c_sbhanu@quicinc.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Julius Werner jwerner@chromium.org Gerrit-CC: Martin L Roth gaumless@gmail.com Gerrit-CC: Paul Menzel paulepanter@mailbox.org Gerrit-MessageType: abandon

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coreboot-gerrit@coreboot.org

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participants (8)

Aaron Durbin (Code Review)
build bot (Jenkins) (Code Review)
Julius Werner (Code Review)
Martin L Roth (Code Review)
mturney mturney (Code Review)
Paul Menzel (Code Review)
Ravi kumar (Code Review)
Sajida Bhanu (Code Review)