Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph.
Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/54960

to look at the new patch set (#14).

Change subject: soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset
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soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset

Further add initial silicon UPD settings for:
- graphics & display
- chipset lockdown
- PAVP
- legacy timer
- PCH master gating control
- HECI

This CL also enables HECI 1 in devicetree.cb.

Signed-off-by: Lean Sheng Tan 
Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed
---
M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
M src/soc/intel/elkhartlake/fsp_params.c
2 files changed, 63 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/54960/14