Change in coreboot[master]: nb/intel/i945: Add macro for device 0:01.0

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27307

Change subject: nb/intel/i945: Add macro for device 0:01.0
......................................................................

nb/intel/i945: Add macro for device 0:01.0

Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/i945.h
2 files changed, 20 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/27307/1

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 7de2c73..c741e51 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -575,25 +575,25 @@
     */

/* First we reset the secondary bus */
-	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
+	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
    reg16 |= (1 << 6); /* SRESET */
-	pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
+	pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
    /* Read back and clear reset bit. */
-	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
+	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
    reg16 &= ~(1 << 6); /* SRESET */
-	pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
+	pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);

-	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
+	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS);
    printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
    if (!(reg16 & 0x48))
    	goto disable_pciexpress_x16_link;
    reg16 |= (1 << 4) | (1 << 0);
-	pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16);
+	pci_write_config16(PCI_DEV(0, 0x01, 0), SLOTSTS, reg16);

-	pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x00);
-	pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x00);
-	pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x0a);
-	pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x0a);
+	pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x00);
+	pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x00);
+	pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x0a);
+	pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x0a);

reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224);
    reg32 &= ~(1 << 8);
@@ -639,12 +639,12 @@
    	reg32 |= 1;
    	pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32);

-		reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
+		reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);

reg16 |= (1 << 6);
-		pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
+		pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
    	reg16 &= ~(1 << 6);
-		pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
+		pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);

printk(BIOS_DEBUG, "PCIe link training ...");
    	timeout = 0x7ffff;
@@ -700,17 +700,17 @@
    /* Enable GPEs */
    reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xec);
    reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */
-	pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32);
+	pci_write_config32(PCI_DEV(0, 0x01, 0), VC0RCTL, reg32);

/* Virtual Channel Configuration: Only VC0 on PCIe x16 */
    reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x114);
    reg32 &= 0xffffff01;
-	pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32);
+	pci_write_config32(PCI_DEV(0, 0x01, 0), VC0RCTL, reg32);

/* Extended VC count */
    reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x104);
    reg32 &= ~(7 << 0);
-	pci_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32);
+	pci_write_config32(PCI_DEV(0, 0x01, 0), VC0RCTL, reg32);

/* Active State Power Management ASPM */

diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index cc5f087..b5e7440 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -84,6 +84,10 @@
 /* Device 0:1.0 PCI configuration space (PCI Express) */

#define BCTRL1		0x3e	/* 16bit */
+#define SBUSN1		0x19	/*  8bit */
+#define SUBUSN1		0x1a	/*  8bit */
+#define SLOTSTS		0xba	/* 16bit */
+#define VC0RCTL		0x114	/* 32bit */
 #define PEGSTS		0x214	/* 32bit */