Change in coreboot[master]: soc/intel/fsp_baytrail: Add VBNV CMOS support

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/25085

Change subject: soc/intel/fsp_baytrail: Add VBNV CMOS support
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soc/intel/fsp_baytrail: Add VBNV CMOS support

* Add VBNV CMOS fsp_baytrail SoC support.
* Add VBOOT_VBNV_CMOS to opencellular rotundu.

Change-Id: I2c1075f8e579c546edb4ff0581764a6a6aa7e89a
Signed-off-by: zaolin 
---
M src/mainboard/opencellular/rotundu/Kconfig
M src/soc/intel/fsp_baytrail/Makefile.inc
M src/soc/intel/fsp_baytrail/include/soc/pmc.h
M src/soc/intel/fsp_baytrail/pmutil.c
4 files changed, 34 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/25085/1

diff --git a/src/mainboard/opencellular/rotundu/Kconfig b/src/mainboard/opencellular/rotundu/Kconfig
index 79b67fb..65c43d0 100644
--- a/src/mainboard/opencellular/rotundu/Kconfig
+++ b/src/mainboard/opencellular/rotundu/Kconfig
@@ -34,6 +34,7 @@

config VBOOT
    select MRC_CACHE_FMAP
+	select VBOOT_VBNV_CMOS
    select GBB_FLAG_DISABLE_LID_SHUTDOWN
    select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
    select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index e01a944..0cf99de 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -42,6 +42,7 @@
 ramstage-y += ramstage.c
 ramstage-y += gpio.c
 romstage-y += gpio.c
+romstage-y += pmutil.c
 ramstage-y += pmutil.c
 ramstage-y += southcluster.c
 romstage-y += reset.c
diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h
index 9bafdc2..16705cf 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h
@@ -290,6 +290,9 @@
 static inline void southcluster_log_state(void) {}
 #endif

+/* Return non-zero when RTC failure happened. */
+int rtc_failure(void);
+
 #endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */

#endif /* _BAYTRAIL_PMC_H_ */
diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c
index a588412..ee99917 100644
--- a/src/soc/intel/fsp_baytrail/pmutil.c
+++ b/src/soc/intel/fsp_baytrail/pmutil.c
@@ -15,18 +15,20 @@

#include <stdint.h>
 #include <arch/io.h>
+#include <cbmem.h>
 #include <console/console.h>

#include <soc/iomap.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
 #include <soc/pmc.h>
+#include <security/vboot/vbnv.h>

-#if defined(__SMM__)
+#if defined(__SIMPLE_DEVICE__)

-static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0);
+static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0);

-static inline pci_devfn_t get_pcu_dev(void)
+static inline device_t get_pcu_dev(void)
 {
    return pcu_dev;
 }
@@ -358,3 +360,27 @@
    write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
    write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts);
 }
+
+int rtc_failure(void)
+{
+	uint32_t gen_pmcon1;
+	int rtc_fail;
+	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+
+	if (ps != NULL)
+		gen_pmcon1 = ps->gen_pmcon1;
+	else
+		gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
+
+	rtc_fail = !!(gen_pmcon1 & RPS);
+
+	if (rtc_fail)
+		printk(BIOS_DEBUG, "RTC failure.\n");
+
+	return rtc_fail;
+}
+
+int vbnv_cmos_failed(void)
+{
+	return rtc_failure();
+}