Change in coreboot[master]: soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55098 )

Change subject: soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them
......................................................................

soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them

Move locking CPU MSRs during CPU init instead of using
CONFIG_PARALLEL_MP_AP_WORK functions.

The AES Lock enable bit caused CPU exception errors as this should not
run on HT siblings. The set_aesni_lock() function takes care of that.

Change-Id: I21598c3e9a153dce25a09b187ddf9cf6363039d3
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/cpx/cpu.c
2 files changed, 10 insertions(+), 18 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/55098/1

diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 9164b7c..19bf2af 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -14,7 +14,6 @@
 #include <soc/acpi.h>
 #include <soc/chip_common.h>
 #include <soc/cpu.h>
-#include <soc/msr.h>
 #include <soc/pch.h>
 #include <soc/ramstage.h>
 #include <soc/p2sb.h>
@@ -144,22 +143,6 @@

}

-static void set_msr_locks(void *unused)
-{
-	/* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions */
-	msr_t msr;
-
-	/* Lock Turbo */
-	msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO);
-	msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK);
-	wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr);
-
-	/* Lock AES enable */
-	msr = rdmsr(MSR_FEATURE_CONFIG);
-	msr.lo |= FEATURE_CONFIG_LOCK;
-	wrmsr(MSR_FEATURE_CONFIG, msr);
-}
-
 static void set_imc_locks(void)
 {
    struct device *dev = 0;
@@ -182,7 +165,6 @@
    /* LOCK PAM */
    pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0);

-	mp_run_on_all_cpus(set_msr_locks, NULL);
    set_pcu_locks();
    set_imc_locks();
    set_upi_locks();
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index 339bf09..37370c1 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -23,6 +23,7 @@
 #include <soc/soc_util.h>
 #include <soc/smmrelocate.h>
 #include <soc/util.h>
+#include <soc/pci_devs.h>

#include "chip.h"

@@ -103,6 +104,15 @@

/* Enable Vmx */
    set_vmx_and_lock();
+	set_aesni_lock();
+
+	/*
+	 * The MSRs and CSRS have the same register layout. Use the CSRS bit definitions
+	 * Lock Turbo. Did FSP-S set this up???
+	 */
+	msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO);
+	msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK);
+	wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr);
 }

static struct device_operations cpu_dev_ops = {