Change in coreboot[master]: soc/amd/cezanne: add devicetree setting for PSPP policy

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Matt Papageorge,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/54930

to look at the new patch set (#3).

Change subject: soc/amd/cezanne: add devicetree setting for PSPP policy
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soc/amd/cezanne: add devicetree setting for PSPP policy

This allows boards to specify which PSPP policy (basically a dynamic
trade-off between power consumption and PCIe link speed) should be used
and also makes sure that the boards are using the expected PSPP policy
and not just the UPD default from the FSP binary that has already
changed once during the development.

BUG=b:188793754

Signed-off-by: Felix Held 
Change-Id: I1b6459b2984711e72b79f5d4d90e04cb4b78d512
---
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fsp_m_params.c
2 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/54930/3