Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
soc/amd/common: Separate single GPIO programming
Do this to reduce indentation a bit. Also it may be desireable to group GPIO configuration such that some GPIOs are handled outside program_gpios() call and would not be included in gpio_list array.
Change-Id: I46cbe33f4d85cd9c7d70f96df82ee9b8ffe50a00 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 63 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/42807/1
diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index b73b836..079bba2 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -200,14 +200,71 @@
__weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {}
-void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) +static void set_single_gpio(const struct soc_amd_gpio *gpio_list_ptr, + struct sci_trigger_regs *sci_trigger_cfg) { uint32_t control, control_flags; - uint8_t mux, index, gpio; + uint8_t mux, gpio; + static const struct soc_amd_event *gev_tbl; + static size_t gev_items; int gevent_num; - const struct soc_amd_event *gev_tbl; + + if (gev_tbl == NULL) + soc_get_gpio_event_table(&gev_tbl, &gev_items); + + gpio = gpio_list_ptr->gpio; + mux = gpio_list_ptr->function; + control = gpio_list_ptr->control; + control_flags = gpio_list_ptr->flags; + + __iomux_write8(gpio, mux & AMD_GPIO_MUX_MASK); + __iomux_read8(gpio); /* Flush posted write */ + + soc_gpio_hook(gpio, mux); + + if (control_flags & GPIO_SPECIAL_FLAG) { + gevent_num = get_gpio_gevent(gpio, gev_tbl, gev_items); + if (gevent_num < 0) { + printk(BIOS_WARNING, "Warning: GPIO pin %d has" + " no associated gevent!\n", gpio); + continue; + } + switch (control_flags & GPIO_SPECIAL_MASK) { + case GPIO_DEBOUNCE_FLAG: + __gpio_setbits32(gpio, GPIO_DEBOUNCE_MASK, control); + break; + case GPIO_WAKE_FLAG: + __gpio_setbits32(gpio, INT_WAKE_MASK, control); + break; + case GPIO_INT_FLAG: + __gpio_setbits32(gpio, AMD_GPIO_CONTROL_MASK, control); + break; + case GPIO_SMI_FLAG: + __gpio_setbits32(gpio, INT_SCI_SMI_MASK, control); + + program_smi(control_flags & FLAGS_TRIGGER_MASK, gevent_num); + break; + case GPIO_SCI_FLAG: + __gpio_setbits32(gpio, INT_SCI_SMI_MASK, control); + + fill_sci_trigger(control_flags & FLAGS_TRIGGER_MASK, gevent_num, + &sci_trigger_cfg); + soc_route_sci(gevent_num); + break; + default: + printk(BIOS_WARNING, "Error, flags 0x%08x\n", + control_flags); + break; + } + } else { + __gpio_setbits32(gpio, AMD_GPIO_CONTROL_MASK, control); + } +} + +void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) +{ struct sci_trigger_regs sci_trigger_cfg = { }; - size_t gev_items; + size_t index;
/* * Disable blocking wake/interrupt status generation while updating @@ -221,57 +278,8 @@ */ master_switch_clr(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN);
- soc_get_gpio_event_table(&gev_tbl, &gev_items); - - for (index = 0; index < size; index++) { - gpio = gpio_list_ptr[index].gpio; - mux = gpio_list_ptr[index].function; - control = gpio_list_ptr[index].control; - control_flags = gpio_list_ptr[index].flags; - - __iomux_write8(gpio, mux & AMD_GPIO_MUX_MASK); - __iomux_read8(gpio); /* Flush posted write */ - - soc_gpio_hook(gpio, mux); - - if (control_flags & GPIO_SPECIAL_FLAG) { - gevent_num = get_gpio_gevent(gpio, gev_tbl, gev_items); - if (gevent_num < 0) { - printk(BIOS_WARNING, "Warning: GPIO pin %d has" - " no associated gevent!\n", gpio); - continue; - } - switch (control_flags & GPIO_SPECIAL_MASK) { - case GPIO_DEBOUNCE_FLAG: - __gpio_setbits32(gpio, GPIO_DEBOUNCE_MASK, control); - break; - case GPIO_WAKE_FLAG: - __gpio_setbits32(gpio, INT_WAKE_MASK, control); - break; - case GPIO_INT_FLAG: - __gpio_setbits32(gpio, AMD_GPIO_CONTROL_MASK, control); - break; - case GPIO_SMI_FLAG: - __gpio_setbits32(gpio, INT_SCI_SMI_MASK, control); - - program_smi(control_flags & FLAGS_TRIGGER_MASK, gevent_num); - break; - case GPIO_SCI_FLAG: - __gpio_setbits32(gpio, INT_SCI_SMI_MASK, control); - - fill_sci_trigger(control_flags & FLAGS_TRIGGER_MASK, gevent_num, - &sci_trigger_cfg); - soc_route_sci(gevent_num); - break; - default: - printk(BIOS_WARNING, "Error, flags 0x%08x\n", - control_flags); - break; - } - } else { - __gpio_setbits32(gpio, AMD_GPIO_CONTROL_MASK, control); - } - } + for (index = 0; index < size; index++) + set_single_gpio(&gpio_list_ptr[index], &sci_trigger_cfg);
/* * Re-enable interrupt status generation.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42807/1/src/soc/amd/common/block/gp... File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/1/src/soc/amd/common/block/gp... PS1, Line 203: set_single_gpio How about program_gpio
https://review.coreboot.org/c/coreboot/+/42807/1/src/soc/amd/common/block/gp... PS1, Line 203: gpio_list_ptr This is no longer a list pointer
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42807/1/src/soc/amd/common/block/gp... File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/1/src/soc/amd/common/block/gp... PS1, Line 203: gpio_list_ptr
This is no longer a list pointer
See CB:42691
Patchset #4 there requsted some minimal visual change as intermediate step, if I understood Aaron correctly.
https://review.coreboot.org/c/coreboot/+/42807/1/src/soc/amd/common/block/gp... PS1, Line 230: continue; return;
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42807
to look at the new patch set (#2).
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
soc/amd/common: Separate single GPIO programming
Do this to reduce indentation a bit. Also it may be desireable to group GPIO configuration such that some GPIOs are handled outside program_gpios() call and would not be included in gpio_list array.
Change-Id: I46cbe33f4d85cd9c7d70f96df82ee9b8ffe50a00 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 63 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/42807/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42807/1/src/soc/amd/common/block/gp... File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/1/src/soc/amd/common/block/gp... PS1, Line 230: continue;
return;
Done
https://review.coreboot.org/c/coreboot/+/42807/2/src/soc/amd/common/block/gp... File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/2/src/soc/amd/common/block/gp... PS2, Line 251: &sci_trigger_cfg); *sigh* drop &
Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Abandoned
CB:42875 is better approach
Kyösti Mälkki has restored this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Restored
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42807
to look at the new patch set (#3).
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
soc/amd/common: Separate single GPIO programming
Do this to reduce indentation a bit. Also it may be desireable to group GPIO configuration such that some GPIOs are handled outside program_gpios() call and would not be included in gpio_list array.
Change-Id: I46cbe33f4d85cd9c7d70f96df82ee9b8ffe50a00 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 46 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/42807/3
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42807/4/src/soc/amd/common/block/gp... File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/4/src/soc/amd/common/block/gp... PS4, Line 195: soc_gpio_hook(gpio, mux); Can we get rid of this? Or replace with some assert to remove those soc_route_sci() calls inside soc_gpio_hook() implementation.
I find it somewhat intrusive that soc/ has this implicit override to change PAD_NF() to PAD_SCI() for GPIO_2. Or something like that, I could not exactly tell what this does.
Hello build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42807
to look at the new patch set (#5).
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
soc/amd/common: Separate single GPIO programming
Do this to reduce indentation a bit. Also it may be desireable to group GPIO configuration such that some GPIOs are handled outside program_gpios() call and would not be included in gpio_list array.
Change-Id: I46cbe33f4d85cd9c7d70f96df82ee9b8ffe50a00 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 50 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/42807/5
Hello build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42807
to look at the new patch set (#6).
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
soc/amd/common: Separate single GPIO programming
Do this to reduce indentation a bit. Also it may be desireable to group GPIO configuration such that some GPIOs are handled outside program_gpios() call and would not be included in gpio_list array.
Change-Id: I46cbe33f4d85cd9c7d70f96df82ee9b8ffe50a00 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 50 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/42807/6
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Patch Set 6: Code-Review+2
Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Abandoned
Kyösti Mälkki has restored this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Restored
Hello build bot (Jenkins), Furquan Shaikh, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42807
to look at the new patch set (#7).
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
soc/amd/common: Separate single GPIO programming
Do this to reduce indentation a bit. Also it may be desireable to group GPIO configuration such that some GPIOs are handled outside program_gpios() call and would not be included in gpio_list array.
Change-Id: I46cbe33f4d85cd9c7d70f96df82ee9b8ffe50a00 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 53 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/42807/7
Attention is currently required from: Raul Rangel. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Patch Set 10:
(3 comments)
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/comment/a67a4ff6_05288835 PS1, Line 203: gpio_list_ptr
See CB:42691 […]
Ack
https://review.coreboot.org/c/coreboot/+/42807/comment/75a1fbd6_7e1e89eb PS1, Line 203: set_single_gpio
How about program_gpio
While true, I also find it visually too much like program_gpios.
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/comment/aba70dbc_9cca9452 PS2, Line 251: &sci_trigger_cfg);
*sigh* drop &
Ack
Attention is currently required from: Kyösti Mälkki, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Patch Set 10:
(2 comments)
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/comment/e313bb7e_46e78b2d PS10, Line 184: gpio_list_ptr Remove list from the name?
https://review.coreboot.org/c/coreboot/+/42807/comment/c82944b0_e75d9dc8 PS10, Line 184: set_single_gpio how about program_single_gpio? set makes me think of setting the value.
Attention is currently required from: Raul Rangel, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Patch Set 10:
(2 comments)
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/comment/587dedf4_154fe119 PS10, Line 184: gpio_list_ptr
Remove list from the name?
Already ack'd the same comment in patchset #1.
https://review.coreboot.org/c/coreboot/+/42807/comment/8c491ccd_b4e1caef PS10, Line 184: set_single_gpio
how about program_single_gpio? set makes me think of setting the value.
Feel free to change it, I don't plan to.
Attention is currently required from: Raul Rangel, Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Patch Set 10:
(4 comments)
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/comment/bc6999a4_0f5dd237 PS1, Line 203: set_single_gpio
While true, I also find it visually too much like program_gpios.
Ack
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/comment/3263151a_b85c0fca PS4, Line 195: soc_gpio_hook(gpio, mux);
Can we get rid of this? Or replace with some assert to remove those soc_route_sci() calls inside soc […]
yeah, calling soc_route_sci in soc_gpio_hook is rather unexpected. as far as i've seen the code in soc_gpio_hook was added to make sure that if gpio 2 is configured as wake pin (pin mux setting 0) the corresponding sci gets configured. introducing a PAD_NF_SCI macro and using that instead of the PAD_NF + soc_gpio_hook magic for the wake pin would allow removing the soc_gpio_hook. do you want to look into that or do you want me to open in internal ticket to look into that later?
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/comment/92d573b4_ca48f0db PS10, Line 184: gpio_list_ptr
Already ack'd the same comment in patchset #1.
the next patch changes this and since it reduces the noise in this patch, i consider this being a good idea
https://review.coreboot.org/c/coreboot/+/42807/comment/a340ad09_9e71f400 PS10, Line 184: set_single_gpio
Feel free to change it, I don't plan to.
changing this to program_single_gpio sounds like a good idea to me, but i'm ok with doing that in a follow-up patch
Attention is currently required from: Raul Rangel, Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Patch Set 10: Code-Review+1
(1 comment)
Patchset:
PS10: looks good to me and there's only one question left
Attention is currently required from: Raul Rangel, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Patch Set 10:
(2 comments)
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/comment/29e454cc_d2d32d40 PS4, Line 195: soc_gpio_hook(gpio, mux);
yeah, calling soc_route_sci in soc_gpio_hook is rather unexpected. […]
Addressing this is not within the scope, I restored CB:43049.
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/comment/2180cc55_a7d5fd4f PS10, Line 184: set_single_gpio
changing this to program_single_gpio sounds like a good idea to me, but i'm ok with doing that in a […]
Ack
Attention is currently required from: Raul Rangel, Kyösti Mälkki, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Patch Set 10: Code-Review+1
Attention is currently required from: Raul Rangel, Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
Patch Set 10: Code-Review+2
(1 comment)
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42807/comment/7a81b6b9_97912276 PS4, Line 195: soc_gpio_hook(gpio, mux);
Addressing this is not within the scope, I restored CB:43049.
Ack. I'd say that i've outlined a good solution to get rid of soc_gpio_hook and will look into that on the other patch
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42807 )
Change subject: soc/amd/common: Separate single GPIO programming ......................................................................
soc/amd/common: Separate single GPIO programming
Do this to reduce indentation a bit. Also it may be desireable to group GPIO configuration such that some GPIOs are handled outside program_gpios() call and would not be included in gpio_list array.
Change-Id: I46cbe33f4d85cd9c7d70f96df82ee9b8ffe50a00 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42807 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 53 insertions(+), 43 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 5b0111b..ebd74e0 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -181,16 +181,62 @@
__weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {}
-void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) +static void set_single_gpio(const struct soc_amd_gpio *gpio_list_ptr, + struct sci_trigger_regs *sci_trigger_cfg) { uint32_t control, control_flags; - uint8_t mux, index, gpio; + uint8_t mux, gpio; + static const struct soc_amd_event *gev_tbl; + static size_t gev_items; int gevent_num; - const struct soc_amd_event *gev_tbl; - struct sci_trigger_regs sci_trigger_cfg = { 0 }; - size_t gev_items; const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_SEPARATE_VERSTAGE); + + gpio = gpio_list_ptr->gpio; + mux = gpio_list_ptr->function; + control = gpio_list_ptr->control; + control_flags = gpio_list_ptr->flags; + + iomux_write8(gpio, mux & AMD_GPIO_MUX_MASK); + iomux_read8(gpio); /* Flush posted write */ + + soc_gpio_hook(gpio, mux); + + gpio_setbits32(gpio, PAD_CFG_MASK, control); + /* Clear interrupt and wake status (write 1-to-clear bits) */ + gpio_or32(gpio, GPIO_INT_STATUS | GPIO_WAKE_STATUS); + if (control_flags == 0) + return; + + /* Can't set SMI flags from PSP */ + if (!can_set_smi_flags) + return; + + if (gev_tbl == NULL) + soc_get_gpio_event_table(&gev_tbl, &gev_items); + + gevent_num = get_gpio_gevent(gpio, gev_tbl, gev_items); + if (gevent_num < 0) { + printk(BIOS_WARNING, "Warning: GPIO pin %d has no associated gevent!\n", + gpio); + return; + } + + if (control_flags & GPIO_FLAG_SMI) { + program_smi(control_flags, gevent_num); + } else if (control_flags & GPIO_FLAG_SCI) { + fill_sci_trigger(control_flags, gevent_num, sci_trigger_cfg); + soc_route_sci(gevent_num); + } +} + +void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) +{ + struct sci_trigger_regs sci_trigger_cfg = { 0 }; + const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && + ENV_SEPARATE_VERSTAGE); + size_t i; + if (!gpio_list_ptr || !size) return;
@@ -206,44 +252,8 @@ */ master_switch_clr(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN);
- if (can_set_smi_flags) - soc_get_gpio_event_table(&gev_tbl, &gev_items); - - for (index = 0; index < size; index++) { - gpio = gpio_list_ptr[index].gpio; - mux = gpio_list_ptr[index].function; - control = gpio_list_ptr[index].control; - control_flags = gpio_list_ptr[index].flags; - - iomux_write8(gpio, mux & AMD_GPIO_MUX_MASK); - iomux_read8(gpio); /* Flush posted write */ - - soc_gpio_hook(gpio, mux); - - gpio_setbits32(gpio, PAD_CFG_MASK, control); - /* Clear interrupt and wake status (write 1-to-clear bits) */ - gpio_or32(gpio, GPIO_INT_STATUS | GPIO_WAKE_STATUS); - if (control_flags == 0) - continue; - - /* Can't set SMI flags from PSP */ - if (!can_set_smi_flags) - continue; - - gevent_num = get_gpio_gevent(gpio, gev_tbl, gev_items); - if (gevent_num < 0) { - printk(BIOS_WARNING, "Warning: GPIO pin %d has no associated gevent!\n", - gpio); - continue; - } - - if (control_flags & GPIO_FLAG_SMI) { - program_smi(control_flags, gevent_num); - } else if (control_flags & GPIO_FLAG_SCI) { - fill_sci_trigger(control_flags, gevent_num, &sci_trigger_cfg); - soc_route_sci(gevent_num); - } - } + for (i = 0; i < size; i++) + set_single_gpio(&gpio_list_ptr[i], &sci_trigger_cfg);
/* * Re-enable interrupt status generation.
-
Angel Pons (Code Review) -
Felix Held (Code Review)
-
Kyösti Mälkki (Code Review)
-
Raul Rangel (Code Review)