Change in coreboot[master]: soc/intel/cannonlake: Use ACPI timer config from soc common code
Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/cannonlake: Use ACPI timer config from soc common code ......................................................................
soc/intel/cannonlake: Use ACPI timer config from soc common code
Replace the usage of structure member "PMTimerDisabled" of struct "soc_intel_cannonlake_config" in soc code with ACPI timer config defined under soc/intel/common/block/timer/Kconfig.
BUG=none TEST=none
Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c 6 files changed, 4 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36064/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7382209..d7c975f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -56,8 +56,6 @@ # putting it under register "common_soc_config" in overridetree.cb file. register "common_soc_config.pch_thermal_trip" = "77"
- register "PmTimerDisabled" = "1" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 6846594..22a8a40 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -179,7 +179,7 @@ const struct soc_intel_cannonlake_config *config; config = config_of_soc();
- if (!config->PmTimerDisabled) { + if (CONFIG_USE_ACPI_PM_TIMER) { fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->pm_tmr_len = 4; fadt->x_pm_tmr_blk.space_id = 1; diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b937699..29ce25a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -267,7 +267,6 @@ * 0x02000000 - 32MiB and beyond */ uint32_t PrmrrSize; - uint8_t PmTimerDisabled;
/* * SLP_S3 Minimum Assertion Width Policy diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index c58b9ad..bfb6bd1 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -390,7 +390,7 @@ config = config_of_soc();
/* Enable PM timer emulation only if ACPI PM timer is disabled */ - if (!config->PmTimerDisabled) + if (CONFIG_USE_ACPI_PM_TIMER) return; /* * The derived frequency is calculated as follows: diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 115b732..3ffc942 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -86,7 +86,7 @@ */ config = config_of_soc(); pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { + if (!CONFIG_USE_ACPI_PM_TIMER) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); reg8 |= (1 << 1); write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index b580620..2dd85ed 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -380,7 +380,7 @@ params->SataPwrOptEnable = config->satapwroptimize;
/* Disable PCH ACPI timer */ - params->EnableTcoTimer = !config->PmTimerDisabled; + params->EnableTcoTimer = CONFIG_USE_ACPI_PM_TIMER;
/* Apply minimum assertion width settings if non-zero */ if (config->PchPmSlpS3MinAssert)
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/cannonlake: Use ACPI timer config from soc common code ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/36064/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36064/1//COMMIT_MSG@9 PS1, Line 9: of in
https://review.coreboot.org/c/coreboot/+/36064/1//COMMIT_MSG@10 PS1, Line 10: ACPI ACPI PM
https://review.coreboot.org/c/coreboot/+/36064/1//COMMIT_MSG@14 PS1, Line 14: none Verify build and boot on hatch?
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36064
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Use ACPI timer config from soc common code ......................................................................
soc/intel/cannonlake: Use ACPI timer config from soc common code
Replace the usage of structure member "PMTimerDisabled" in struct "soc_intel_cannonlake_config" in soc code with ACPI PM timer config defined under soc/intel/common/block/timer/Kconfig.
BUG=none TEST=Verify build and boot on helios.
Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c 6 files changed, 4 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36064/2
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/cannonlake: Use ACPI timer config from soc common code ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/36064/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36064/1//COMMIT_MSG@9 PS1, Line 9: of
in
Done
https://review.coreboot.org/c/coreboot/+/36064/1//COMMIT_MSG@10 PS1, Line 10: ACPI
ACPI PM
Done
https://review.coreboot.org/c/coreboot/+/36064/1//COMMIT_MSG@14 PS1, Line 14: none
Verify build and boot on hatch?
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/cannonlake: Use ACPI timer config from soc common code ......................................................................
Patch Set 2:
Hello Meera,
please keep all the platforms supporting this aligned. skylake/ and icelake/ also have a switch to disable the ACPI timer, so they should all use the same Kconfig mechanism.
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36064
to look at the new patch set (#3).
Change subject: soc/intel/cannonlake: Use ACPI PM timer config from soc common code ......................................................................
soc/intel/cannonlake: Use ACPI PM timer config from soc common code
Replace the usage of structure member "PMTimerDisabled" in struct "soc_intel_cannonlake_config" in soc code with ACPI PM timer config defined under soc/intel/common/block/timer/Kconfig.
BUG=none TEST=Verify build and boot on helios.
Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c 6 files changed, 4 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36064/3
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/cannonlake: Use ACPI PM timer config from soc common code ......................................................................
Patch Set 3:
Patch Set 2:
Hello Meera,
please keep all the platforms supporting this aligned. skylake/ and icelake/ also have a switch to disable the ACPI timer, so they should all use the same Kconfig mechanism.
Hello Nico,
Sure, Will take care and push CLs for the same. Thank you.
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36064
to look at the new patch set (#4).
Change subject: soc/intel/cannonlake: Use ACPI timer config from soc common code ......................................................................
soc/intel/cannonlake: Use ACPI timer config from soc common code
Replace the usage of structure member "PMTimerDisabled" of struct "soc_intel_cannonlake_config" in soc code with ACPI timer config defined under soc/intel/common/block/timer/Kconfig.
BUG=none TEST=none
Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c 6 files changed, 4 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36064/4
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36064
to look at the new patch set (#5).
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code
Replace the usage of structure member "PMTimerDisabled" of struct "soc_intel_{cnl,skl,icl,tgl}_config" in soc code with ACPI timer config defined under soc/intel/common/block/timer/Kconfig.
BUG=none TEST=none
Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 16 files changed, 16 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36064/5
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36064
to look at the new patch set (#6).
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code
Replace the usage of structure member "PMTimerDisabled" of struct "soc_intel_{cnl,skl,icl,tgl}_config" in soc code with ACPI timer config defined under soc/intel/common/block/timer/Kconfig.
BUG=none TEST=none
Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 16 files changed, 10 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36064/6
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36064/6/src/soc/intel/tigerlake/fin... File src/soc/intel/tigerlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/36064/6/src/soc/intel/tigerlake/fin... PS6, Line 94: CONFIG_ENABLE_ACPI_PM_TIMER use the CONFIG macro around Kconfig options
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36064
to look at the new patch set (#7).
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code
Replace the usage of structure member "PMTimerDisabled" of struct "soc_intel_{cnl,skl,icl,tgl}_config" in soc code with ACPI timer config defined under soc/intel/common/block/timer/Kconfig.
BUG=none TEST=none
Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/sentry/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 30 files changed, 10 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36064/7
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36064/6/src/soc/intel/tigerlake/fin... File src/soc/intel/tigerlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/36064/6/src/soc/intel/tigerlake/fin... PS6, Line 94: CONFIG_ENABLE_ACPI_PM_TIMER
use the CONFIG macro around Kconfig options
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
Patch Set 7: Code-Review+1
Looks like a few boards are failing:
GOOGLE_EVE INTEL_KBLRVP11 INTEL_KBLRVP3 INTEL_KBLRVP7 INTEL_KBLRVP8 INTEL_KUNIMITSU INTEL_SKLSDLBRK RAZER_BLADE_STEALTH_KBL ASROCK_H110M_DVS PURISM_LIBREM13_V2 PURISM_LIBREM13_V4 PURISM_LIBREM15_V3 PURISM_LIBREM15_V4
Hello Patrick Rudolph, Angel Pons, Subrata Banik, Aamir Bohra, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36064
to look at the new patch set (#8).
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code
Replace the usage of structure member "PMTimerDisabled" of struct "soc_intel_{cnl,skl,icl,tgl}_config" in soc code with ACPI timer config defined under soc/intel/common/block/timer/Kconfig.
BUG=none TEST=none
Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/sentry/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 41 files changed, 10 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36064/8
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
Patch Set 8:
boards with pmtimerdisabled=0 would now need to select the ACPI_PM_TIMER Kconfig from mainboard Kconfig. Else pm timer support would be removed from those boards , with current changes.
Hello Patrick Rudolph, Angel Pons, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36064
to look at the new patch set (#9).
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code
Replace the usage of structure member "PMTimerDisabled" of struct "soc_intel_{cnl,skl,icl,tgl}_config" in soc code with ACPI timer config defined under soc/intel/common/block/timer/Kconfig.
BUG=none TEST=none
Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/sentry/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/Kconfig M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 46 files changed, 15 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36064/9
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
Patch Set 9:
Patch Set 8:
boards with pmtimerdisabled=0 would now need to select the ACPI_PM_TIMER Kconfig from mainboard Kconfig. Else pm timer support would be removed from those boards , with current changes.
Agreed. Done
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
Patch Set 9:
Patch Set 7: Code-Review+1
Looks like a few boards are failing:
GOOGLE_EVE INTEL_KBLRVP11 INTEL_KBLRVP3 INTEL_KBLRVP7 INTEL_KBLRVP8 INTEL_KUNIMITSU INTEL_SKLSDLBRK RAZER_BLADE_STEALTH_KBL ASROCK_H110M_DVS PURISM_LIBREM13_V2 PURISM_LIBREM13_V4 PURISM_LIBREM15_V3 PURISM_LIBREM15_V4
Thank you. Resolved.
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36064/9/src/mainboard/intel/kblrvp/... File src/mainboard/intel/kblrvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/36064/9/src/mainboard/intel/kblrvp/... PS9, Line 19: ENABLE_ACPI_PM_TIMER from earlier code, I see not all RVPs are supporting ACPI PM timer
Hello Patrick Rudolph, Angel Pons, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36064
to look at the new patch set (#10).
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code
Replace the usage of structure member "PMTimerDisabled" of struct "soc_intel_{cnl,skl,icl,tgl}_config" in soc code with ACPI timer config defined under soc/intel/common/block/timer/Kconfig.
BUG=none TEST=none
Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/sentry/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/Kconfig M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 46 files changed, 15 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36064/10
Hello Patrick Rudolph, Angel Pons, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36064
to look at the new patch set (#11).
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code
Replace the usage of structure member "PMTimerDisabled" of struct "soc_intel_{cnl,skl,icl,tgl}_config" in soc code with ACPI timer config defined under soc/intel/common/block/timer/Kconfig.
BUG=none TEST=none
Change-Id: I42fcf23523889d43f0491fad662ca6b3597ab348 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/sentry/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/Kconfig M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 46 files changed, 15 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36064/11
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
Patch Set 11: Code-Review+1
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
Patch Set 11: Code-Review+2
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
Patch Set 11: Code-Review+2
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
Patch Set 11: Code-Review-1
(2 comments)
There's no need to select a user configurable Kconfig at mainboard level.
https://review.coreboot.org/c/coreboot/+/36064/11/src/soc/intel/cannonlake/f... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/36064/11/src/soc/intel/cannonlake/f... PS11, Line 394: params->EnableTcoTimer = CONFIG_ENABLE_ACPI_PM_TIMER; CONFIG(ENABLE_ACPI_PM_TIMER)
https://review.coreboot.org/c/coreboot/+/36064/11/src/soc/intel/skylake/chip... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/36064/11/src/soc/intel/skylake/chip... PS11, Line 275: params->EnableTcoTimer = CONFIG_ENABLE_ACPI_PM_TIMER; CONFIG(ENABLE_ACPI_PM_TIMER)
Meera Ravindranath has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36064 )
Change subject: soc/intel/{cnl,skl,icl,tgl}: Use ACPI timer config from soc common code ......................................................................
Abandoned
Found a better mechanism to handle PM timer. Porting https://review.coreboot.org/c/coreboot/+/23510/ to icl,cnl and tgl
-
Aamir Bohra (Code Review) -
Angel Pons (Code Review)
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Arthur Heymans (Code Review)
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Maulik V Vaghela (Code Review)
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Meera Ravindranath (Code Review)
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Nico Huber (Code Review)
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Patrick Rudolph (Code Review)