Change in coreboot[master]: soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definition

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21001

Change subject: soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definition
......................................................................

soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definition

LPC pci config register BIOS Control (BC) - offset 0xDC bit 1
is for Lock Down.

Change-Id: I4780d2e41c833c0146640f715759dbb0a948c4ab
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/include/soc/lpc.h
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/21001/1

diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h
index 3488ee2..3ea9be9 100644
--- a/src/soc/intel/cannonlake/include/soc/lpc.h
+++ b/src/soc/intel/cannonlake/include/soc/lpc.h
@@ -48,7 +48,7 @@
 #define LGMR			0x98 /* LPC Generic Memory Range */
 #define BIOS_CNTL		0xdc
 #define   LPC_BC_BILD		(1 << 7) /* BILD */
-#define   LPC_BC_LE		(1 << 2) /* LE */
+#define   LPC_BC_LE		(1 << 1) /* LE */
 #define   LPC_BC_EISS		(1 << 5) /* EISS */
 #define PCCTL			0xE0 /* PCI Clock Control */
 #define   CLKRUN_EN		(1 << 0)