[S] Change in coreboot[main]: mb/google/brya/var/xol: Add VGPIO configurations for CPU PCIe RP

[Subrata Banik (Code Review)]

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, SH Kim.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81033?usp=email )

Change subject: mb/google/brya/var/xol: Add VGPIO configurations for CPU PCIe RP
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Patch Set 1:

(2 comments)

File src/mainboard/google/brya/variants/xol/gpio.c:

https://review.coreboot.org/c/coreboot/+/81033/comment/3252955b_d87179a6 :
PS1, Line 197: /*Add virtual GPIOs for CPU PCIe RP*/
> I just copied this GPIO group from https://review.coreboot.org/c/coreboot/+/57875. I was able to get a hint from this comment, how about keep it?

the code commenting is not proper here as space is required around the statement.

https://review.coreboot.org/c/coreboot/+/81033/comment/03812fd2_5cc20d60 :
PS1, Line 198: 	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
> I just copied it from https://review.coreboot.org/c/coreboot/+/57875. NVME couldn't work properly without this CL, so the chipset default config should not be native function.
> I couldn't find the reference for vGPIOs, can you look at the bug - b:200886824? (Can I get access for this bug as well?)

you should have access now.

```
We have root cause that this hang is due to the vGPIO is not set correctly, without setting those pins for PEG60,  CPU cannot communicate with PCH about the clkreq state (since clock source is in PCH)
```