[S] Change in coreboot[master]: vc/amd/fsp/mendocino:Add fch_usb_3_port_force_gen1 tp AGESA FSP-M UPD

[Patrick Huang (Code Review)]

Patrick Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73915 )

Change subject: vc/amd/fsp/mendocino:Add fch_usb_3_port_force_gen1 tp AGESA FSP-M UPD
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vc/amd/fsp/mendocino:Add fch_usb_3_port_force_gen1 tp AGESA FSP-M UPD

To add fch_usb_3_port_force_gen1 parameter to force usb3 port to gen1

BUG=b:273841155
BRANCH=None
TEST=Build

Change-Id: I7560abb9a5fda6af3c2814f8b26c92925d8c17f4
Signed-off-by: Patrick Huang 
---
M src/vendorcode/amd/fsp/mendocino/FspmUpd.h
1 file changed, 18 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/73915/1

diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h
index bed13af..f7ac83a 100644
--- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h
@@ -100,7 +100,8 @@
    /** Offset 0x04DD**/	uint32_t                    vrm_current_limit_mA;
    /** Offset 0x04E1**/	uint32_t                    vrm_maximum_current_limit_mA;
    /** Offset 0x04E5**/	uint32_t                    vrm_soc_current_limit_mA;
-	/** Offset 0x04E9**/	uint8_t                     UnusedUpdSpace2[279];
+	/** Offset 0x04E9**/	uint8_t                     fch_usb_3_port_force_gen1;
+	/** Offset 0x04EA**/	uint8_t                     UnusedUpdSpace2[278];
    /** Offset 0x0600**/	uint16_t                    UpdTerminator;
 } FSP_M_CONFIG;