Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13445
-gerrit
commit 05ac32aaaca2ef4bbaa6fa81187e128c37e2bd2b Author: Lee Leahy leroy.p.leahy@intel.com Date: Thu Feb 4 18:05:42 2016 -0800
soc/intel/quark: Enable Serial Port
Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Note that the BIST value is always zero as validated in esram_init.inc * The initial TSC value is currently not saved!
Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select ENABLE_DEBUG_LED_TEMPRAMINIT" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing.
Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0 Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/soc/intel/quark/Kconfig | 36 ++++++++++++++++++++++ src/soc/intel/quark/Makefile.inc | 4 +++ src/soc/intel/quark/include/soc/iomap.h | 27 +++++++++++++++++ src/soc/intel/quark/include/soc/pci_devs.h | 26 ++++++++++++++++ src/soc/intel/quark/include/soc/romstage.h | 29 ++++++++++++++++++ src/soc/intel/quark/romstage/Makefile.inc | 2 ++ src/soc/intel/quark/romstage/cache_as_ram.inc | 43 ++++++++++++++++++++++++++- src/soc/intel/quark/romstage/uart.c | 42 ++++++++++++++++++++++++++ src/soc/intel/quark/tsc_freq.c | 36 ++++++++++++++++++++++ src/soc/intel/quark/uart.c | 43 +++++++++++++++++++++++++++ 10 files changed, 287 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 002e1d3..5642c77 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -26,6 +26,9 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select SOC_INTEL_COMMON + select TSC_CONSTANT_RATE + select UDELAY_TSC select USE_MARCH_586
config ADD_FSP_PDAT_FILE @@ -63,6 +66,21 @@ config CBFS_SIZE This option specifies the maximum size of the CBFS portion in the firmware image.
+config DCACHE_RAM_BASE + hex + default 0x80070000 + +config DCACHE_RAM_SIZE + hex + default 0x00008000 + +config ENABLE_BUILTIN_HSUART1 + bool "Enable built-in HSUART1" + default n + help + The Quark SoC has two HSUART. Choose this option to configure the pads + and enable HSUART1, which can be used for the debug console. + config ENABLE_DEBUG_LED bool default n @@ -142,6 +160,12 @@ config FSP_ESRAM_LOC help The location in ESRAM where a copy of the FSP binary is placed.
+config INTEL_UART_SPECIFIC_OPTIONS + def_bool y + depends on ENABLE_BUILTIN_HSUART1 + select NO_UART_ON_SUPERIO + select DRIVERS_UART_8250MEM_32 + config RMU_FILE string default "3rdparty/blobs/soc/intel/quark/rmu.bin" @@ -157,4 +181,16 @@ config RMU_LOC The location in CBFS that the RMU is located. It must match the strap-determined base address.
+config TTYS0_BASE + hex "HSUART1 Base Address" + depends on ENABLE_BUILTIN_HSUART1 + default 0xA0019000 + help + Memory mapped MMIO of HSUART1. + +config TTYS0_LCS + int + depends on ENABLE_BUILTIN_HSUART1 + default 3 + endif # SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 880f1d4..915360a 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -19,8 +19,12 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc
romstage-y += memmap.c +romstage-y += tsc_freq.c +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
ramstage-y += memmap.c +ramstage-y += tsc_freq.c +ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/quark/include
diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h new file mode 100644 index 0000000..f033dcb --- /dev/null +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_IOMAP_H_ +#define _QUARK_IOMAP_H_ + +/* + * Memory Mapped IO base addresses. + */ + +/* UART MMIO */ +#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE + +#endif /* _QUARK_IOMAP_H_ */ diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h new file mode 100644 index 0000000..0543a05 --- /dev/null +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_PCI_DEVS_H_ +#define _QUARK_PCI_DEVS_H_ + +/* IO Fabric 1 */ +#define SIO1_DEV 0x14 +# define HSUART1_DEV SIO1_DEV +# define HSUART1_FUNC 5 + +#endif /* _QUARK_PCI_DEVS_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h new file mode 100644 index 0000000..a35f4a6 --- /dev/null +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_ROMSTAGE_H_ +#define _QUARK_ROMSTAGE_H_ + +#if !defined(__PRE_RAM__) +#error "Don't include romstage.h from a ramstage compilation unit!" +#endif + +#include <fsp/util.h> + +int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); + +#endif /* _QUARK_ROMSTAGE_H_ */ diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index cb17d3d..518c6a5 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -15,3 +15,5 @@
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc + +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc index fd94607..698f383 100644 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -114,7 +114,48 @@ CAR_init_done: jmp . #endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
- clrl %eax + /* Setup bootloader stack */ + movl %edx, %esp + + /* + * eax: 0 + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * esp: Top of stack in temp RAM + */ + + /* Create cache_as_ram_params on stack */ + pushl %edx /* bootloader CAR end */ + pushl %ecx /* bootloader CAR begin */ + pushl %ebp /* FSP_INFO_HEADER */ + pushl %edi /* bist */ +// movd %mm1, %eax + pushl %eax /* tsc[63:32] */ +// movd %mm0, %eax + pushl %eax /* tsc[31:0] */ + pushl %esp /* pointer to cache_as_ram_params */ + + /* Save FSP_INFO_HEADER location in ebx */ + mov %ebp, %ebx + + /* Coreboot assumes stack/heap region will be zero */ + cld + movl %ecx, %edi + neg %ecx + /* Only clear up to current stack value. */ + add %esp, %ecx + shrl $2, %ecx + xorl %eax, %eax + rep stosl + +before_romstage: + post_code(0x2A) + + /* Call cache_as_ram_main(struct cache_as_ram_params *) */ + call cache_as_ram_main + movb $0x69, %ah jmp .Lhlt
halt1: diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c new file mode 100644 index 0000000..2d53a48 --- /dev/null +++ b/src/soc/intel/quark/romstage/uart.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <device/pci.h> +#include <device/pci_def.h> +#include <rules.h> +#include <soc/romstage.h> + +int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base) +{ + uint16_t reg16; + + /* HSUART controller #1 (B0:D20:F5). */ + device_t uart_dev = PCI_DEV(bus, dev, func); + + /* Decode BAR0(offset 0x10). */ + pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base); + + /* Enable MEMBASE at CMD(offset 0x04). */ + reg16 = pci_read_config16(uart_dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(uart_dev, PCI_COMMAND, reg16); + + return 0; +} diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c new file mode 100644 index 0000000..a770c81 --- /dev/null +++ b/src/soc/intel/quark/tsc_freq.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> + +static unsigned long bus_freq_khz(void) +{ + /* cpu freq = 400 MHz */ + return 400 * 1000; +} + +unsigned long tsc_freq_mhz(void) +{ + /* assume ratio=1 */ + unsigned bclk_khz = bus_freq_khz(); + + if (!bclk_khz) + return 0; + + return (bclk_khz * 1) / 1000; +} diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c new file mode 100644 index 0000000..d5e5f3d --- /dev/null +++ b/src/soc/intel/quark/uart.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <console/uart.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <rules.h> +#include <soc/pci_devs.h> + +unsigned int uart_platform_refclk(void) +{ + return 44236800; +} + +uintptr_t uart_platform_base(int idx) +{ + if (idx < 6) { + /* HSUART controller #1 (B0:D20:F5). */ + device_t dev = PCI_DEV(0, HSUART1_DEV, HSUART1_FUNC); + + /* UART base address at BAR0(offset 0x10). */ + return (unsigned int) (pci_read_config32(dev, + PCI_BASE_ADDRESS_0) & ~0xfff); + } + return 0; +}