Change in coreboot[master]: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45002 )

Change subject: soc/intel/{cnl,skl}: Add alignment check for TSEG base and size
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soc/intel/{cnl,skl}: Add alignment check for TSEG base and size

Port commit 14d5991 (soc/intel/icelake: Add alignment check for TSEG
base and size) to remaining SoCs.

Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f
Signed-off-by: Benjamin Doron 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45002
Tested-by: build bot (Jenkins) 
Reviewed-by: Michael Niewöhner 
Reviewed-by: Angel Pons 
---
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/skylake/smmrelocate.c
2 files changed, 12 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Michael Niewöhner: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index 05bd1f7..7d189ea 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -152,6 +152,12 @@
    const u32 rmask = ~(4 * KiB - 1);

smm_region(&tseg_base, &tseg_size);
+
+	if (!IS_ALIGNED(tseg_base, tseg_size)) {
+		printk(BIOS_WARNING, "TSEG base not aligned with TSEG size! Not setting SMRR\n");
+		return;
+	}
+
    smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 05bd1f7..7d189ea 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -152,6 +152,12 @@
    const u32 rmask = ~(4 * KiB - 1);

smm_region(&tseg_base, &tseg_size);
+
+	if (!IS_ALIGNED(tseg_base, tseg_size)) {
+		printk(BIOS_WARNING, "TSEG base not aligned with TSEG size! Not setting SMRR\n");
+		return;
+	}
+
    smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */