Change in coreboot[master]: lib/spd_bin: Correct LPDDR3 SPD information

[EricR Lai (Code Review)]

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

lib/spd_bin: Correct LPDDR3 SPD information

Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on
JEDEC 21-C, LPDDR3 has the same definition with LPDDR4.

Signed-off-by: Eric Lai 
Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c
---
M src/lib/spd_bin.c
1 file changed, 15 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39366/1

diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index a1d75ef..45b1b4c 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -32,7 +32,16 @@

static bool is_memory_type_ddr4(int dram_type)
 {
-	return (dram_type == SPD_DRAM_DDR4);
+	switch (dram_type) {
+	case SPD_DRAM_DDR3:
+	case SPD_DRAM_LPDDR3_INTEL:
+		return false;
+	/* LPDDR3, LPDDR4 and DDR4 are share the same attributes */
+	case SPD_DRAM_LPDDR3_JEDEC:
+	case SPD_DRAM_DDR4:
+	case SPD_DRAM_LPDDR4:
+		return true;
+	}
 }

static const char *spd_get_module_type_string(int dram_type)
@@ -57,14 +66,14 @@
    static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 };
    int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf;
    switch (dram_type) {
-	/* DDR3 and LPDDR3 has the same bank definition */
+	/* DDR3 and LPDDR3_Intel have the same bank definition */
    case SPD_DRAM_DDR3:
    case SPD_DRAM_LPDDR3_INTEL:
-	case SPD_DRAM_LPDDR3_JEDEC:
    	if (index >= ARRAY_SIZE(ddr3_banks))
    		return -1;
    	return ddr3_banks[index];
-	/* DDR4 and LPDDR4 has the same bank definition */
+	/* LPDDR3, LPDDR4 and DDR4 have the same bank definition */
+	case SPD_DRAM_LPDDR3_JEDEC:
    case SPD_DRAM_DDR4:
    case SPD_DRAM_LPDDR4:
    	if (index >= ARRAY_SIZE(ddr4_banks))
@@ -144,11 +153,12 @@
    	spd_name[DDR3_SPD_PART_LEN] = 0;
    	break;
    case SPD_DRAM_LPDDR3_INTEL:
-	case SPD_DRAM_LPDDR3_JEDEC:
    	memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF],
    		LPDDR3_SPD_PART_LEN);
    	spd_name[LPDDR3_SPD_PART_LEN] = 0;
    	break;
+	/* LPDDR3, LPDDR4 and DDR4 have the same part number offset */
+	case SPD_DRAM_LPDDR3_JEDEC:
    case SPD_DRAM_DDR4:
    case SPD_DRAM_LPDDR4:
    	memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN);

[EricR Lai (Code Review)]

EricR Lai has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

lib/spd_bin: Correct LPDDR3 SPD information

Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on
JEDEC 21-C, LPDDR3 has the same definition with LPDDR4.

Signed-off-by: Eric Lai 
Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c
---
M src/lib/spd_bin.c
1 file changed, 15 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39366/2

[EricR Lai (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39366

to look at the new patch set (#3).

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

lib/spd_bin: Correct LPDDR3 SPD information

Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on
JEDEC 21-C, LPDDR3 has the same definition with LPDDR4.

Signed-off-by: Eric Lai 
Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c
---
M src/lib/spd_bin.c
1 file changed, 16 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39366/3

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 3:

Furquan, I can't find the spec of Intel LPDDR3. But I think it is the fake SPD like DDR3 right?

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39366/3/src/lib/spd_bin.c 
File src/lib/spd_bin.c:

https://review.coreboot.org/c/coreboot/+/39366/3/src/lib/spd_bin.c@33 
PS3, Line 33: is_memory_type_ddr4
I think this should be named something like "use_ddr4_params" since the memory type is not really ddr4 but still it is using the params/attributes same as ddr4.

https://review.coreboot.org/c/coreboot/+/39366/3/src/lib/spd_bin.c@36 
PS3, Line 36: case SPD_DRAM_DDR3:
            : 	case SPD_DRAM_LPDDR3_INTEL:
            : 		return false;
            : 	/* LPDDR3, LPDDR4 and DDR4 share the same attributes */
            : 	case SPD_DRAM_LPDDR3_JEDEC:
            : 	case SPD_DRAM_DDR4:
            : 	case SPD_DRAM_LPDDR4:
            : 	default:
            : 		return true;
Just use --

case SPD_DRAM_LPDDR3_JEDEC:
case SPD_DRAM_DDR4:
case SPD_DRAM_LPDDR4:
    return true;
default:
    return false;

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39366/3/src/lib/spd_bin.c 
File src/lib/spd_bin.c:

https://review.coreboot.org/c/coreboot/+/39366/3/src/lib/spd_bin.c@33 
PS3, Line 33: is_memory_type_ddr4
> I think this should be named something like "use_ddr4_params" since the memory type is not really dd […]

That's fair enough.

https://review.coreboot.org/c/coreboot/+/39366/3/src/lib/spd_bin.c@36 
PS3, Line 36: case SPD_DRAM_DDR3:
            : 	case SPD_DRAM_LPDDR3_INTEL:
            : 		return false;
            : 	/* LPDDR3, LPDDR4 and DDR4 share the same attributes */
            : 	case SPD_DRAM_LPDDR3_JEDEC:
            : 	case SPD_DRAM_DDR4:
            : 	case SPD_DRAM_LPDDR4:
            : 	default:
            : 		return true;
> Just use -- […]

We can consider which is popular and seems new generation will apply DDR4 or new to me. So I want use  ddr4 as default.

[EricR Lai (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39366

to look at the new patch set (#4).

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

lib/spd_bin: Correct LPDDR3 SPD information

Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on
JEDEC 21-C, LPDDR3 has the same definition with LPDDR4.

Signed-off-by: Eric Lai 
Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c
---
M src/lib/spd_bin.c
1 file changed, 22 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39366/4

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39366/3/src/lib/spd_bin.c 
File src/lib/spd_bin.c:

https://review.coreboot.org/c/coreboot/+/39366/3/src/lib/spd_bin.c@33 
PS3, Line 33: is_memory_type_ddr4
> That's fair enough.

Done

https://review.coreboot.org/c/coreboot/+/39366/3/src/lib/spd_bin.c@36 
PS3, Line 36: case SPD_DRAM_DDR3:
            : 	case SPD_DRAM_LPDDR3_INTEL:
            : 		return false;
            : 	/* LPDDR3, LPDDR4 and DDR4 share the same attributes */
            : 	case SPD_DRAM_LPDDR3_JEDEC:
            : 	case SPD_DRAM_DDR4:
            : 	case SPD_DRAM_LPDDR4:
            : 	default:
            : 		return true;
> We can consider which is popular and seems new generation will apply DDR4 or new to me. […]

Done

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39366/3/src/lib/spd_bin.c 
File src/lib/spd_bin.c:

https://review.coreboot.org/c/coreboot/+/39366/3/src/lib/spd_bin.c@36 
PS3, Line 36: case SPD_DRAM_DDR3:
            : 	case SPD_DRAM_LPDDR3_INTEL:
            : 		return false;
            : 	/* LPDDR3, LPDDR4 and DDR4 share the same attributes */
            : 	case SPD_DRAM_LPDDR3_JEDEC:
            : 	case SPD_DRAM_DDR4:
            : 	case SPD_DRAM_LPDDR4:
            : 	default:
            : 		return true;
> We can consider which is popular and seems new generation will apply DDR4 or new to me. […]

How about:

case SPD_DRAM_DDR3:
case SPD_DRAM_LPDDR3_INTEL:
    return false;
/* LPDDR3, LPDDR4 and DDR4 share the same attributes */
case SPD_DRAM_LPDDR3_JEDEC:
case SPD_DRAM_DDR4:
case SPD_DRAM_LPDDR4:
    return true;
default:
    printk(BIOS_ERR,"Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n", dram_type, __func__);
    return true;

[EricR Lai (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39366

to look at the new patch set (#5).

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

lib/spd_bin: Correct LPDDR3 SPD information

Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on
JEDEC 21-C, LPDDR3 has the same definition with LPDDR4.

Signed-off-by: Eric Lai 
Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c
---
M src/lib/spd_bin.c
1 file changed, 26 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39366/5

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39366/5/src/lib/spd_bin.c 
File src/lib/spd_bin.c:

https://review.coreboot.org/c/coreboot/+/39366/5/src/lib/spd_bin.c@45 
PS5, Line 45: 		printk(BIOS_ERR,"Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n",
space required after that ',' (ctx:VxV)

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39366/3/src/lib/spd_bin.c 
File src/lib/spd_bin.c:

https://review.coreboot.org/c/coreboot/+/39366/3/src/lib/spd_bin.c@36 
PS3, Line 36: case SPD_DRAM_DDR3:
            : 	case SPD_DRAM_LPDDR3_INTEL:
            : 		return false;
            : 	/* LPDDR3, LPDDR4 and DDR4 share the same attributes */
            : 	case SPD_DRAM_LPDDR3_JEDEC:
            : 	case SPD_DRAM_DDR4:
            : 	case SPD_DRAM_LPDDR4:
            : 	default:
            : 		return true;
> How about: […]

Sure, better.

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39366/5/src/lib/spd_bin.c 
File src/lib/spd_bin.c:

https://review.coreboot.org/c/coreboot/+/39366/5/src/lib/spd_bin.c@45 
PS5, Line 45: 		printk(BIOS_ERR,"Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n",
> space required after that ',' (ctx:VxV)

Ack

[EricR Lai (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39366

to look at the new patch set (#6).

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

lib/spd_bin: Correct LPDDR3 SPD information

Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on
JEDEC 21-C, LPDDR3 has the same definition with LPDDR4.

Signed-off-by: Eric Lai 
Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c
---
M src/lib/spd_bin.c
1 file changed, 26 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39366/6

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39366/6/src/lib/spd_bin.c 
File src/lib/spd_bin.c:

https://review.coreboot.org/c/coreboot/+/39366/6/src/lib/spd_bin.c@45 
PS6, Line 45: 		printk(BIOS_ERR,"Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n",
space required after that ',' (ctx:VxV)

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39366/6/src/lib/spd_bin.c 
File src/lib/spd_bin.c:

https://review.coreboot.org/c/coreboot/+/39366/6/src/lib/spd_bin.c@45 
PS6, Line 45: 		printk(BIOS_ERR,"Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n",
> space required after that ',' (ctx:VxV)

Ack

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 6:

@Furquan, please take a look if you have time :)

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 6: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/39366/6/src/lib/spd_bin.c 
File src/lib/spd_bin.c:

https://review.coreboot.org/c/coreboot/+/39366/6/src/lib/spd_bin.c@45 
PS6, Line 45: 		printk(BIOS_ERR,"Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n",
> Ack

Was this addressed? I don't see an updated patchset.

[EricR Lai (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39366

to look at the new patch set (#7).

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

lib/spd_bin: Correct LPDDR3 SPD information

Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on
JEDEC 21-C, LPDDR3 has the same definition with LPDDR4.

Signed-off-by: Eric Lai 
Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c
---
M src/lib/spd_bin.c
1 file changed, 26 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39366/7

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39366/6/src/lib/spd_bin.c 
File src/lib/spd_bin.c:

https://review.coreboot.org/c/coreboot/+/39366/6/src/lib/spd_bin.c@45 
PS6, Line 45: 		printk(BIOS_ERR,"Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n",
> Was this addressed? I don't see an updated patchset.

oh, I finally find the error.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

Patch Set 7: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39366 )

Change subject: lib/spd_bin: Correct LPDDR3 SPD information
......................................................................

lib/spd_bin: Correct LPDDR3 SPD information

Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on
JEDEC 21-C, LPDDR3 has the same definition with LPDDR4.

Signed-off-by: Eric Lai 
Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39366
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/lib/spd_bin.c
1 file changed, 26 insertions(+), 12 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index 84e2123..35bcb4c 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -30,9 +30,22 @@
    	}
 }

-static bool is_memory_type_ddr4(int dram_type)
+static bool use_ddr4_params(int dram_type)
 {
-	return (dram_type == SPD_DRAM_DDR4);
+	switch (dram_type) {
+	case SPD_DRAM_DDR3:
+	case SPD_DRAM_LPDDR3_INTEL:
+		return false;
+	/* LPDDR3, LPDDR4 and DDR4 share the same attributes */
+	case SPD_DRAM_LPDDR3_JEDEC:
+	case SPD_DRAM_DDR4:
+	case SPD_DRAM_LPDDR4:
+		return true;
+	default:
+		printk(BIOS_ERR, "Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n",
+			dram_type, __func__);
+		return true;
+	}
 }

static const char *spd_get_module_type_string(int dram_type)
@@ -57,14 +70,14 @@
    static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 };
    int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf;
    switch (dram_type) {
-	/* DDR3 and LPDDR3 have the same bank definition */
+	/* DDR3 and LPDDR3_Intel have the same bank definition */
    case SPD_DRAM_DDR3:
    case SPD_DRAM_LPDDR3_INTEL:
-	case SPD_DRAM_LPDDR3_JEDEC:
    	if (index >= ARRAY_SIZE(ddr3_banks))
    		return -1;
    	return ddr3_banks[index];
-	/* DDR4 and LPDDR4 has the same bank definition */
+	/* LPDDR3, LPDDR4 and DDR4 have the same bank definition */
+	case SPD_DRAM_LPDDR3_JEDEC:
    case SPD_DRAM_DDR4:
    case SPD_DRAM_LPDDR4:
    	if (index >= ARRAY_SIZE(ddr4_banks))
@@ -106,8 +119,8 @@
 static int spd_get_ranks(const uint8_t spd[], int dram_type)
 {
    static const int spd_ranks[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
-	int organ_offset = is_memory_type_ddr4(dram_type) ? DDR4_ORGANIZATION
-							: DDR3_ORGANIZATION;
+	int organ_offset = use_ddr4_params(dram_type) ? DDR4_ORGANIZATION
+						      : DDR3_ORGANIZATION;
    int index = (spd[organ_offset] >> 3) & 7;
    if (index >= ARRAY_SIZE(spd_ranks))
    	return -1;
@@ -117,8 +130,8 @@
 static int spd_get_devw(const uint8_t spd[], int dram_type)
 {
    static const int spd_devw[4]  = { 4, 8, 16, 32 };
-	int organ_offset = is_memory_type_ddr4(dram_type) ? DDR4_ORGANIZATION
-							: DDR3_ORGANIZATION;
+	int organ_offset = use_ddr4_params(dram_type) ? DDR4_ORGANIZATION
+						      : DDR3_ORGANIZATION;
    int index = spd[organ_offset] & 7;
    if (index >= ARRAY_SIZE(spd_devw))
    	return -1;
@@ -128,8 +141,8 @@
 static int spd_get_busw(const uint8_t spd[], int dram_type)
 {
    static const int spd_busw[4]  = { 8, 16, 32, 64 };
-	int busw_offset = is_memory_type_ddr4(dram_type) ? DDR4_BUS_DEV_WIDTH
-							: DDR3_BUS_DEV_WIDTH;
+	int busw_offset = use_ddr4_params(dram_type) ? DDR4_BUS_DEV_WIDTH
+						     : DDR3_BUS_DEV_WIDTH;
    int index = spd[busw_offset] & 7;
    if (index >= ARRAY_SIZE(spd_busw))
    	return -1;
@@ -144,11 +157,12 @@
    	spd_name[DDR3_SPD_PART_LEN] = 0;
    	break;
    case SPD_DRAM_LPDDR3_INTEL:
-	case SPD_DRAM_LPDDR3_JEDEC:
    	memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF],
    		LPDDR3_SPD_PART_LEN);
    	spd_name[LPDDR3_SPD_PART_LEN] = 0;
    	break;
+	/* LPDDR3, LPDDR4 and DDR4 have the same part number offset */
+	case SPD_DRAM_LPDDR3_JEDEC:
    case SPD_DRAM_DDR4:
    case SPD_DRAM_LPDDR4:
    	memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN);