Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61606 )
Change subject: vc/amd/cezanne: Add support to map UARTs ......................................................................
vc/amd/cezanne: Add support to map UARTs
This will allow coreboot to directly write to the UART controller.
BUG=b:215599230 TEST=Try mapping the uart on guybrush
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ibd346cec2994e612f2901bb91d572982ce2ed5e7 --- M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/61606/1
diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h index 4cf9e70..d88bfe1 100644 --- a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h @@ -88,10 +88,17 @@ FCH_IO_DEVICE_MISC, FCH_IO_DEVICE_AOAC, FCH_IO_DEVICE_IOPORT, + FCH_IO_DEVICE_UART,
FCH_IO_DEVICE_END, };
+enum fch_uart_id { + FCH_UART_ID_0 = 0, + FCH_UART_ID_1 = 1, + FCH_UART_ID_MAX, +}; + enum fch_i2c_controller_id { FCH_I2C_CONTROLLER_ID_0 = 0, FCH_I2C_CONTROLLER_ID_1 = 1,