Change in coreboot[master]: vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v31...

[Saurabh Mishra (Code Review)]

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63707 )

Change subject: vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v3133.00
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vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v3133.00

The headers added are generated as per FSP v3133.00
Previous FSP version was v3054.02
Changes Include:
- UPD Enable eMMC Controller Offset Added in FspsUpd.h
- UPD UnusedUpdSpace Name Update in FspmUpd.h

BUG=b:229062240
BRANCH=None
TEST=Build with "emerge-nissa intel-adlnfsp" and boot check Nivviks.
Change-Id: I7b921e2aa467597a1c764fc554e2e83e5bb542e8
Signed-off-by: Saurabh Mishra 
---
M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
2 files changed, 4 insertions(+), 56 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/63707/1

diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h
index a687eb0..3734598 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h
@@ -3222,7 +3222,7 @@

/** Offset 0x0B38
 **/
-  UINT8                       UnusedUpdSpace34[6];
+  UINT8                       UnusedUpdSpace33[6];

/** Offset 0x0B3E
 **/
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
index b7cb818..4bcf61b 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h
@@ -3865,61 +3865,9 @@
 **/
   UINT32                      FspEventHandler;

-/** Offset 0x0FD4 - Enable eMMC Controller
-  Enable/disable eMMC Controller.
-  $EN_DIS
+/** Offset 0x0FD4 - Reserved
 **/
-  UINT8                       ScsEmmcEnabled;
-
-/** Offset 0x0FD5 - Enable eMMC HS400 Mode
-  Enable eMMC HS400 Mode.
-  $EN_DIS
-**/
-  UINT8                       ScsEmmcHs400Enabled;
-
-/** Offset 0x0FD6 - Use DLL values from policy
-  Set if FSP should use HS400 DLL values from policy
-  $EN_DIS
-**/
-  UINT8                       EmmcUseCustomDlls;
-
-/** Offset 0x0FD7 - Reserved
-**/
-  UINT8                       Reserved56;
-
-/** Offset 0x0FD8 - Emmc Tx CMD Delay control register value
-  Please see Tx CMD Delay Control register definition for help
-**/
-  UINT32                      EmmcTxCmdDelayRegValue;
-
-/** Offset 0x0FDC - Emmc Tx DATA Delay control 1 register value
-  Please see Tx DATA Delay control 1 register definition for help
-**/
-  UINT32                      EmmcTxDataDelay1RegValue;
-
-/** Offset 0x0FE0 - Emmc Tx DATA Delay control 2 register value
-  Please see Tx DATA Delay control 2 register definition for help
-**/
-  UINT32                      EmmcTxDataDelay2RegValue;
-
-/** Offset 0x0FE4 - Emmc Rx CMD + DATA Delay control 1 register value
-  Please see Rx CMD + DATA Delay control 1 register definition for help
-**/
-  UINT32                      EmmcRxCmdDataDelay1RegValue;
-
-/** Offset 0x0FE8 - Emmc Rx CMD + DATA Delay control 2 register value
-  Please see Rx CMD + DATA Delay control 2 register definition for help
-**/
-  UINT32                      EmmcRxCmdDataDelay2RegValue;
-
-/** Offset 0x0FEC - Emmc Rx Strobe Delay control register value
-  Please see Rx Strobe Delay control register definition for help
-**/
-  UINT32                      EmmcRxStrobeDelayRegValue;
-
-/** Offset 0x0FF0 - Reserved
-**/
-  UINT8                      Reserved57[69];
+  UINT8                       Reserved56[97];

/** Offset 0x1035 - Enable VMD Global Mapping
   Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
@@ -3929,7 +3877,7 @@

/** Offset 0x1036 - Reserved
 **/
-  UINT8                       Reserved58[122];
+  UINT8                       Reserved57[122];
 } FSP_S_CONFIG;

/** Fsp S UPD Configuration