Rizwan Qureshi (rizwan.qureshi@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18319
-gerrit
commit 92f00d631c09374ed2debc6e1d6cc5483304d92e Author: Rizwan Qureshi rizwan.qureshi@intel.com Date: Fri Feb 10 15:58:24 2017 +0530
soc/intel/skylake: Add option to disable host reads to PMC XRAM
PMC XRAM registers should be readable. FSP disables the access to these registers by default. But, it also exposes a UPD to enable/disable host reads to PMC XRAM, expose the same in devicetree as a config option.
Change-Id: Iaa33aa3233bda4f050da37d1d8af0556311c9496 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- src/mainboard/google/poppy/devicetree.cb | 3 +++ src/soc/intel/skylake/chip.h | 3 +++ src/soc/intel/skylake/chip_fsp20.c | 2 ++ 3 files changed, 8 insertions(+)
diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 200b092..1d8dd7a 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -52,6 +52,9 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" register "SendVrMbxCmd" = "1" # IMVP8 workaround + #When set to true, this disallows host reads to PMC XRAM + register "PchPmPmcReadDisable" = "0" +
register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 2e4adb2..81b2170 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -385,6 +385,9 @@ struct soc_intel_skylake_config { */ u32 PrmrrSize;
+ /* When set to true, this disallows host reads to PMC XRAM */ + u8 PchPmPmcReadDisable; + /* Statically clock gate 8254 PIT. */ u8 clock_gate_8254;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index e8ff2fa..62a595a 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -240,6 +240,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) */ params->SendVrMbxCmd1 = config->SendVrMbxCmd;
+ tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; + soc_irq_settings(params); }