Change in coreboot[master]: soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40757 )

Change subject: soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree
......................................................................

soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree

This CL adds support to fill PcieRpClkReqDetect UPD from devicetree.
Filling this UPD will allow FSP to enable proper clksrc gpio
configuration.

BUG=None
BRANCH=None
TEST=Build and boot jslrvp with NVMe

Change-Id: Iad0b394fea019223a5b98fff0cb4a2bd1d2a7bd7
Signed-off-by: Meera Ravindranath 
---
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
2 files changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/40757/1

diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 3983d03..a6932bc 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -110,6 +110,9 @@
     * clksrc. */
    uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];

+	/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
+	uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
+
    /* PCIe RP L1 substate */
    enum L1_substates_control {
    	L1_SS_FSP_DEFAULT,
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 19b9300..f525fd8 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -104,6 +104,10 @@
    /* disable Legacy PME */
    memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));

+	/* Enable ClkReqDetect for enabled port */
+	memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
+		sizeof(config->PcieRpClkReqDetect));
+
    /* USB configuration */
    for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {

[Ronak Kanabar (Code Review)]

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40757 )

Change subject: soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree
......................................................................

Patch Set 1: Code-Review+1

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40757 )

Change subject: soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree
......................................................................

Patch Set 1: Code-Review+2

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40757 )

Change subject: soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree
......................................................................

Patch Set 1: Code-Review+2

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40757 )

Change subject: soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree
......................................................................

Patch Set 1: Code-Review+2

[Ronak Kanabar (Code Review)]

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40757 )

Change subject: soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree
......................................................................

Patch Set 1: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40757 )

Change subject: soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree
......................................................................

soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree

This CL adds support to fill PcieRpClkReqDetect UPD from devicetree.
Filling this UPD will allow FSP to enable proper clksrc gpio
configuration.

BUG=None
BRANCH=None
TEST=Build and boot jslrvp with NVMe

Change-Id: Iad0b394fea019223a5b98fff0cb4a2bd1d2a7bd7
Signed-off-by: Meera Ravindranath 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40757
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
Reviewed-by: V Sowmya 
Reviewed-by: Maulik V Vaghela 
Reviewed-by: Ronak Kanabar 
---
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
2 files changed, 7 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  V Sowmya: Looks good to me, approved
  Maulik V Vaghela: Looks good to me, approved
  Ronak Kanabar: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 3983d03..a6932bc 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -110,6 +110,9 @@
     * clksrc. */
    uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];

+	/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
+	uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
+
    /* PCIe RP L1 substate */
    enum L1_substates_control {
    	L1_SS_FSP_DEFAULT,
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 19b9300..f525fd8 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -104,6 +104,10 @@
    /* disable Legacy PME */
    memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));

+	/* Enable ClkReqDetect for enabled port */
+	memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
+		sizeof(config->PcieRpClkReqDetect));
+
    /* USB configuration */
    for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40757 )

Change subject: soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetree
......................................................................

Patch Set 2:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2988
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2987
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2986
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/2985

Please note: This test is under development and might not be accurate at all!