Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46912 )
Change subject: cpu/intel/haswell: Do not determine CPU type at runtime ......................................................................
cpu/intel/haswell: Do not determine CPU type at runtime
It is already known at compile-time.
Change-Id: I20303cd1f79b71268a9d734c85a1291afe9177e9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 4 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46912/1
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 0701332..deadbc5 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -145,8 +145,9 @@ int cpu_config_tdp_levels(void);
/* CPU identification */ -int haswell_family_model(void); -int haswell_stepping(void); -int haswell_is_ult(void); +static inline int haswell_is_ult(void) +{ + return CONFIG(INTEL_LYNXPOINT_LP); +}
#endif diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 4b73c6a..15dcff5 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -186,27 +186,6 @@ [0x11] = 128, };
-int haswell_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -int haswell_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -/* Dynamically determine if the part is ULT. */ -int haswell_is_ult(void) -{ - static int ult = -1; - - if (ult < 0) - ult = !!(haswell_family_model() == HASWELL_FAMILY_ULT); - - return ult; -} - /* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46912
to look at the new patch set (#6).
Change subject: cpu/intel/haswell: Do not determine CPU type at runtime ......................................................................
cpu/intel/haswell: Do not determine CPU type at runtime
It is already known at compile-time.
Change-Id: I20303cd1f79b71268a9d734c85a1291afe9177e9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 4 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46912/6
Attention is currently required from: Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46912 )
Change subject: cpu/intel/haswell: Do not determine CPU type at runtime ......................................................................
Patch Set 13: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46912 )
Change subject: cpu/intel/haswell: Do not determine CPU type at runtime ......................................................................
cpu/intel/haswell: Do not determine CPU type at runtime
It is already known at compile-time.
Change-Id: I20303cd1f79b71268a9d734c85a1291afe9177e9 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46912 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 4 insertions(+), 24 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 0701332..deadbc5 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -145,8 +145,9 @@ int cpu_config_tdp_levels(void);
/* CPU identification */ -int haswell_family_model(void); -int haswell_stepping(void); -int haswell_is_ult(void); +static inline int haswell_is_ult(void) +{ + return CONFIG(INTEL_LYNXPOINT_LP); +}
#endif diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 4b73c6a..15dcff5 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -186,27 +186,6 @@ [0x11] = 128, };
-int haswell_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -int haswell_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -/* Dynamically determine if the part is ULT. */ -int haswell_is_ult(void) -{ - static int ult = -1; - - if (ult < 0) - ult = !!(haswell_family_model() == HASWELL_FAMILY_ULT); - - return ult; -} - /* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46912 )
Change subject: cpu/intel/haswell: Do not determine CPU type at runtime ......................................................................
Patch Set 14:
Automatic boot test returned (PASS/FAIL/TOTAL): 7/1/8 "ThinkPad T500" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/35836 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/35835 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/35834 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/35833 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/35832 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/35831 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/35829 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/35828
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Angel Pons (Code Review)
-
Nico Huber (Code Review)