Change in coreboot[master]: cpu/intel/haswell: Allow use of TSC for the monotonic timer

[Tristan Corrick (Code Review)]

Hello build bot (Jenkins), Nico Huber,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/29383

to look at the new patch set (#2).

Change subject: cpu/intel/haswell: Allow use of TSC for the monotonic timer
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cpu/intel/haswell: Allow use of TSC for the monotonic timer

When the Haswell-specific monotonic timer is used on an ASRock H81M-HDS
with a Pentium G3258, the following exception is generated, causing the
system to hang.

CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
    Code: 0 eflags: 00010006 cr2: 00000000
    eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
    edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90

The exception occurs when trying to read `MSR_COUNTER_24_MHz`, located
at 0x637. This MSR only exists on Haswell-ULT CPUs.

So, allow boards to use the TSC monotonic timer instead. They can do
this by placing `select TSC_MONOTONIC_TIMER` in the mainboard Kconfig.

Change-Id: I31d0e801b8cc85330dcb70c3fc03670f2e677e8f
Signed-off-by: Tristan Corrick 
---
M src/cpu/intel/haswell/Makefile.inc
1 file changed, 4 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/29383/2