Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31303
Change subject: device/pci_early.c: Drop some guards ......................................................................
device/pci_early.c: Drop some guards
With PCI_DEV() always defined it is no longer necessary to exclude this code from building.
Change-Id: I58a6348750d240aa6024599f7b1af1449f31e8ac Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/console/init.c M src/device/Makefile.inc M src/device/pci_early.c M src/include/device/pci.h 4 files changed, 6 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31303/1
diff --git a/src/console/init.c b/src/console/init.c index 8aa7d7d..89be51b 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -74,10 +74,9 @@ if (IS_ENABLED(CONFIG_DEBUG_CONSOLE_INIT)) car_set_var(console_inited, 1);
-#if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) - if (!ENV_SMM && !ENV_RAMSTAGE) + if (IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) && + !ENV_SMM && !ENV_RAMSTAGE) pci_early_bridge_init(); -#endif
console_hw_init();
diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index bed0f71..39df1c7 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -13,7 +13,6 @@ ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c -ramstage-$(CONFIG_PCI) += pci_early.c ramstage-$(CONFIG_PCI) += pci_rom.c ramstage-y += smbus_ops.c
@@ -28,12 +27,10 @@ romstage-y += device_const.c ramstage-y += device_const.c
-ifeq ($(CONFIG_ARCH_X86),y) bootblock-$(CONFIG_PCI) += pci_early.c verstage-$(CONFIG_PCI) += pci_early.c romstage-$(CONFIG_PCI) += pci_early.c postcar-$(CONFIG_PCI) += pci_early.c -endif
subdirs-y += oprom dram
diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 4cf8c7e..9086e64 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -18,9 +18,10 @@ #include <arch/io.h> #include <device/pci.h> #include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_type.h> #include <delay.h>
-#if !ENV_RAMSTAGE unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) { unsigned pos = 0; @@ -68,9 +69,6 @@ { return pci_find_next_capability(dev, cap, 0); } -#endif - -#if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE)
static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge) { @@ -167,4 +165,3 @@
pci_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000); } -#endif /* CONFIG_EARLY_PCI_BRIDGE */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index b750205..f0724e0f 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -143,7 +143,6 @@ unsigned int pci_find_capability(struct device *dev, unsigned int cap); #endif /* __SIMPLE_DEVICE__ */
-void pci_early_bridge_init(void); void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); @@ -157,4 +156,6 @@
#endif /* CONFIG_PCI */
+void pci_early_bridge_init(void); + #endif /* PCI_H */
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31303 )
Change subject: device/pci_early.c: Drop some guards ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/31303/2/src/console/init.c File src/console/init.c:
https://review.coreboot.org/#/c/31303/2/src/console/init.c@78 PS2, Line 78: !ENV_SMM && !ENV_RAMSTAGE) would it not fit on one line?
Hello Arthur Heymans, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31303
to look at the new patch set (#3).
Change subject: device/pci_early.c: Drop some guards ......................................................................
device/pci_early.c: Drop some guards
With PCI_DEV() always defined it is no longer necessary to exclude this code from building.
Change-Id: I58a6348750d240aa6024599f7b1af1449f31e8ac Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/console/init.c M src/device/Makefile.inc M src/device/pci_early.c M src/include/device/pci.h 4 files changed, 5 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31303/3
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31303 )
Change subject: device/pci_early.c: Drop some guards ......................................................................
Patch Set 3: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31303 )
Change subject: device/pci_early.c: Drop some guards ......................................................................
device/pci_early.c: Drop some guards
With PCI_DEV() always defined it is no longer necessary to exclude this code from building.
Change-Id: I58a6348750d240aa6024599f7b1af1449f31e8ac Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/31303 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/console/init.c M src/device/Makefile.inc M src/device/pci_early.c M src/include/device/pci.h 4 files changed, 5 insertions(+), 12 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/console/init.c b/src/console/init.c index 8aa7d7d..7d1f31a 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -74,10 +74,8 @@ if (IS_ENABLED(CONFIG_DEBUG_CONSOLE_INIT)) car_set_var(console_inited, 1);
-#if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) - if (!ENV_SMM && !ENV_RAMSTAGE) + if (IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE) pci_early_bridge_init(); -#endif
console_hw_init();
diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index bed0f71..39df1c7 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -13,7 +13,6 @@ ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c -ramstage-$(CONFIG_PCI) += pci_early.c ramstage-$(CONFIG_PCI) += pci_rom.c ramstage-y += smbus_ops.c
@@ -28,12 +27,10 @@ romstage-y += device_const.c ramstage-y += device_const.c
-ifeq ($(CONFIG_ARCH_X86),y) bootblock-$(CONFIG_PCI) += pci_early.c verstage-$(CONFIG_PCI) += pci_early.c romstage-$(CONFIG_PCI) += pci_early.c postcar-$(CONFIG_PCI) += pci_early.c -endif
subdirs-y += oprom dram
diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 4cf8c7e..9086e64 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -18,9 +18,10 @@ #include <arch/io.h> #include <device/pci.h> #include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_type.h> #include <delay.h>
-#if !ENV_RAMSTAGE unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) { unsigned pos = 0; @@ -68,9 +69,6 @@ { return pci_find_next_capability(dev, cap, 0); } -#endif - -#if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE)
static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge) { @@ -167,4 +165,3 @@
pci_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000); } -#endif /* CONFIG_EARLY_PCI_BRIDGE */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index b750205..f0724e0f 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -143,7 +143,6 @@ unsigned int pci_find_capability(struct device *dev, unsigned int cap); #endif /* __SIMPLE_DEVICE__ */
-void pci_early_bridge_init(void); void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); @@ -157,4 +156,6 @@
#endif /* CONFIG_PCI */
+void pci_early_bridge_init(void); + #endif /* PCI_H */
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)