Change in ...coreboot[master]: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30863
Change subject: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup ......................................................................
cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup
Pineview CPU's support a non-eviction mode that ought to be used during cache as ram setup.
Tested on Foxconn D41S, still boots.
Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc 2 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/30863/1
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index d1cc80f..1ea5a34 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -1,5 +1,7 @@ config CPU_INTEL_SOCKET_FCBGA559 bool + help + Select this socket on Intel Pineview
if CPU_INTEL_SOCKET_FCBGA559
diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 7993294..868f6e5 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -8,7 +8,7 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S -postcar-y += ../car/p4-netburst/exit_car.S +cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +postcar-y += ../car/non-evict/exit_car.S
romstage-y += ../car/romstage.c
Hello Kyösti Mälkki, Patrick Rudolph, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30863
to look at the new patch set (#2).
Change subject: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup ......................................................................
cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup
Pineview CPUs support a non-eviction mode that ought to be used during cache as ram setup.
Tested on Foxconn D41S, still boots.
Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc 2 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/30863/2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30863 )
Change subject: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup ......................................................................
Patch Set 1: Code-Review-2
needs to be rebased on top of patch for L2 cache enable
Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30863
to look at the new patch set (#3).
Change subject: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup ......................................................................
cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup
Pineview CPUs support a non-eviction mode that ought to be used during cache as ram setup.
This assumes that all atoms that need to set a special register to enable L2 cache are socketed and hence uses a static Kconfig option to set that MSR on affected CPUs.
Tested on Foxconn D41S, still boots.
Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- A src/cpu/intel/car/non-evict/Kconfig M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc 4 files changed, 23 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/30863/3
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30863 )
Change subject: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup ......................................................................
Patch Set 3: -Code-Review
Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30863
to look at the new patch set (#4).
Change subject: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup ......................................................................
cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup
Pineview CPUs support a non-eviction mode that ought to be used during cache as ram setup.
This assumes that all atoms that need to set a special register to enable L2 cache are socketed and hence uses a static Kconfig option to set that MSR on affected CPUs.
Tested on Foxconn D41S, still boots.
Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/Kconfig A src/cpu/intel/car/non-evict/Kconfig M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc 5 files changed, 24 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/30863/4
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30863 )
Change subject: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/30863/5/src/cpu/intel/car/non-evict/cache_as... File src/cpu/intel/car/non-evict/cache_as_ram.S:
https://review.coreboot.org/#/c/30863/5/src/cpu/intel/car/non-evict/cache_as... PS5, Line 85: movl $0x80000008, %eax You need to check this MSR is always supported for the socket. The check in p4-netburst was more complete.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30863 )
Change subject: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/30863/5/src/cpu/intel/car/non-evict/cache_as... File src/cpu/intel/car/non-evict/cache_as_ram.S:
https://review.coreboot.org/#/c/30863/5/src/cpu/intel/car/non-evict/cache_as... PS5, Line 85: movl $0x80000008, %eax
You need to check this MSR is always supported for the socket. […]
This BGA socket supports pineview or newer CPU's which were released in 2010 and they all support this cpuid.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30863 )
Change subject: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup ......................................................................
Patch Set 5: Code-Review+2
Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30863 )
Change subject: cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup ......................................................................
cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup
Pineview CPUs support a non-eviction mode that ought to be used during cache as ram setup.
This assumes that all atoms that need to set a special register to enable L2 cache are socketed and hence uses a static Kconfig option to set that MSR on affected CPUs.
Tested on Foxconn D41S, still boots.
Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/30863 Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/Kconfig A src/cpu/intel/car/non-evict/Kconfig M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc 5 files changed, 24 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index f5d0ab9..18f73b4 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -36,3 +36,4 @@ source src/cpu/intel/turbo/Kconfig source src/cpu/intel/common/Kconfig source src/cpu/intel/microcode/Kconfig +source src/cpu/intel/car/non-evict/Kconfig diff --git a/src/cpu/intel/car/non-evict/Kconfig b/src/cpu/intel/car/non-evict/Kconfig new file mode 100644 index 0000000..faf13e7 --- /dev/null +++ b/src/cpu/intel/car/non-evict/Kconfig @@ -0,0 +1,5 @@ +config CPU_HAS_L2_ENABLE_MSR + bool + help + Select this in Kconfig of CPU sockets/SOC where the CPU + has an MSR to enable the L2 CPU cache diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index d2beaa7..3203159 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -24,6 +24,7 @@ #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#define NoEvictMod_MSR 0x2e0 +#define BBL_CR_CTL3_MSR 0x11e
.global bootblock_pre_c_entry
@@ -133,6 +134,18 @@ orl $MTRR_DEF_TYPE_EN, %eax wrmsr
+#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR) + /* + * Enable the L2 cache. Currently this assumes that this + * only affect socketed CPU's for which this is always valid, + * hence the static preprocesser. + */ + movl $BBL_CR_CTL3_MSR, %ecx + rdmsr + orl $0x100, %eax + wrmsr +#endif + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index d1cc80f..6566a01 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -1,5 +1,7 @@ config CPU_INTEL_SOCKET_FCBGA559 bool + help + Select this socket on Intel Pineview
if CPU_INTEL_SOCKET_FCBGA559
@@ -8,6 +10,7 @@ select CPU_INTEL_MODEL_106CX select MMX select SSE + select CPU_HAS_L2_ENABLE_MSR
config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 7993294..868f6e5 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -8,7 +8,7 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S -postcar-y += ../car/p4-netburst/exit_car.S +cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +postcar-y += ../car/non-evict/exit_car.S
romstage-y += ../car/romstage.c
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)