Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18526 )
Change subject: binaryPI: Drop CAR teardown without POSTCAR_STAGE
......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/18526/8/src/drivers/amd/agesa/exit_...
File src/drivers/amd/agesa/exit_car.S:
https://review.coreboot.org/c/coreboot/+/18526/8/src/drivers/amd/agesa/exit_...
PS8, Line 32: /* enable cache */
: movl %cr0, %eax
: andl $(~(CR0_CD | CR0_NW)), %eax
: movl %eax, %cr0
It will be followup if we find this is redunant now.
FWIW the code in cache_as_ram.S did not do this either on the postcar path.
CB:37179 removed it in soc/amd/common.
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