[S] Change in coreboot[master]: soc/intel/xeon_sp: Add P2SB definition for SPR-SP

[David Hendricks (Code Review)]

Attention is currently required from: Jonathan Zhang, TimLiu-SMCI, Johnny Lin, Christian Walter, Jian-Ming Wang, Arthur Heymans, Tim Chu.

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72612 )

Change subject: soc/intel/xeon_sp: Add P2SB definition for SPR-SP
......................................................................

Patch Set 1: Code-Review-1

(3 comments)

Patchset:

PS1: 
Need a clarification, otherwise looks good to me.

File src/soc/intel/xeon_sp/include/soc/p2sb.h:

https://review.coreboot.org/c/coreboot/+/72612/comment/450cfbbb_f6781397 
PS1, Line 14: #define P2SBC				0xe0
            : #define SBILOCK				(1 << 31)
Can you double-check these? The closest thing I can find is "Device Hide(HIDE)" bit 8 in the P2SBC Control register at 0xE0, which exists on both LBG and EBG.

I only found SBILOCK mentioned in the EBG BIOS specification (doc #631063), but that is confusing since it says the bit is P2SB PCI offset E3h[7].

https://review.coreboot.org/c/coreboot/+/72612/comment/93a62ac2_db2818d1 
PS1, Line 16: #if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP)
I guess it's overkill to split headers in this case. I guess we can keep it as-is until we find a need for more p2sb registers?