Furquan Shaikh (furquan@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15895
-gerrit
commit 1498fbc3a5a2379a85798733d7e7a6f520c996d9 Author: Furquan Shaikh furquan@google.com Date: Mon Jul 25 16:58:15 2016 -0700
qualcomm/gale: Add required files to enable elog in ramstage
Change-Id: Idbad4f8763be18002907a62be755b2fdf7e479ec Signed-off-by: Furquan Shaikh furquan@google.com --- src/mainboard/google/gale/Makefile.inc | 1 + src/soc/qualcomm/ipq40xx/Makefile.inc | 5 +++++ 2 files changed, 6 insertions(+)
diff --git a/src/mainboard/google/gale/Makefile.inc b/src/mainboard/google/gale/Makefile.inc index 6c7e55f..855e712 100644 --- a/src/mainboard/google/gale/Makefile.inc +++ b/src/mainboard/google/gale/Makefile.inc @@ -39,6 +39,7 @@ ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += mmu.c ramstage-y += reset.c +ramstage-y += blsp.c
bootblock-y += memlayout.ld romstage-y += memlayout.ld diff --git a/src/soc/qualcomm/ipq40xx/Makefile.inc b/src/soc/qualcomm/ipq40xx/Makefile.inc index 8ea28f0..568b0e3 100644 --- a/src/soc/qualcomm/ipq40xx/Makefile.inc +++ b/src/soc/qualcomm/ipq40xx/Makefile.inc @@ -51,6 +51,11 @@ ramstage-y += uart.c # Want the UART always ready for the kernels' earlyprintk ramstage-y += usb.c ramstage-y += tz_wrapper.S
+ramstage-y += blsp.c +ramstage-y += i2c.c +ramstage-y += qup.c +ramstage-y += spi.c + ifeq ($(CONFIG_USE_BLOBS),y)
$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_ELF)) \