Attention is currently required from: Matt DeVillier, Reto Buerki.
Hello Arthur Heymans, Matt DeVillier, Paul Menzel, Sean Rhodes, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79957?usp=email
to look at the new patch set (#2).
Change subject: soc/intel/apollolake: Fix PCI memory resource alloc ......................................................................
soc/intel/apollolake: Fix PCI memory resource alloc
There is a mismatch in how PCI memory resources are allocated on Appollo Lake with the current configuration. While the ACPI code expects resources to be below PCR_BASE_ADDRESS (i.e. PMAX), the coreboot C code allocates them above, leading to the following error messages on Linux:
pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] pci_bus 0000:00: root bus resource [mem 0x80000000-0xd0000000 window] pci_bus 0000:00: root bus resource [mem 0x280000000-0x7fffffffff window] pci 0000:00:13.1: can't claim BAR 14 [mem 0xdeb00000-0xdebfffff]: no compatible bridge window pci 0000:00:13.1: can't claim BAR 15 [mem 0xdec00000-0xdecfffff 64bit pref]: no compatible bridge window pci 0000:00:13.1: BAR 14: assigned [mem 0x80000000-0x800fffff] pci 0000:00:13.1: BAR 15: assigned [mem 0x281300000-0x2813fffff 64bit pref]
Tested on up/squared with Linux kernel version 6.1.0.
Fix this by setting the DOMAIN_RESOURCE_32BIT_LIMIT to PCR_BASE_ADDRESS, and by moving the UART base address into the expected range.
Thanks to Nico Huber for the help in writing this patch.
Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1 Signed-off-by: Reto Buerki reet@codelabs.ch --- M src/soc/intel/apollolake/Kconfig 1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/79957/2