Change in coreboot[master]: arch/x86: Provide readXp/writeXp helpers in arch/mmio.h

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51862 )

Change subject: arch/x86: Provide readXp/writeXp helpers in arch/mmio.h
......................................................................

arch/x86: Provide readXp/writeXp helpers in arch/mmio.h

These p-suffixed helpers allow dropping pointer casts in call-sites,
which is particularly useful when accessing registers at an offset from
a base address. Move existing helpers in chipset code to arch/mmio.h and
create the rest accordingly.

Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862
Reviewed-by: Aaron Durbin 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Patrick Rudolph 
Tested-by: build bot (Jenkins) 
---
M src/arch/x86/include/arch/mmio.h
M src/northbridge/intel/ironlake/raminit.c
M src/southbridge/intel/bd82x6x/early_thermal.c
3 files changed, 40 insertions(+), 25 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, but someone else must approve
  Furquan Shaikh: Looks good to me, but someone else must approve
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h
index c2aa0fb..7188eac 100644
--- a/src/arch/x86/include/arch/mmio.h
+++ b/src/arch/x86/include/arch/mmio.h
@@ -45,4 +45,44 @@
    *((volatile uint64_t *)(addr)) = value;
 }

+static __always_inline uint8_t read8p(const uintptr_t addr)
+{
+	return read8((void *)addr);
+}
+
+static __always_inline uint16_t read16p(const uintptr_t addr)
+{
+	return read16((void *)addr);
+}
+
+static __always_inline uint32_t read32p(const uintptr_t addr)
+{
+	return read32((void *)addr);
+}
+
+static __always_inline uint64_t read64p(const uintptr_t addr)
+{
+	return read64((void *)addr);
+}
+
+static __always_inline void write8p(const uintptr_t addr, const uint8_t value)
+{
+	write8((void *)addr, value);
+}
+
+static __always_inline void write16p(const uintptr_t addr, const uint16_t value)
+{
+	write16((void *)addr, value);
+}
+
+static __always_inline void write32p(const uintptr_t addr, const uint32_t value)
+{
+	write32((void *)addr, value);
+}
+
+static __always_inline void write64p(const uintptr_t addr, const uint64_t value)
+{
+	write64((void *)addr, value);
+}
+
 #endif /* __ARCH_MMIO_H__ */
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index 34e5657..af835e2 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -115,16 +115,6 @@
    return val;
 }

-static void write32p(uintptr_t addr, uint32_t val)
-{
-	write32((void *)addr, val);
-}
-
-static uint32_t read32p(uintptr_t addr)
-{
-	return read32((void *)addr);
-}
-
 static void sfence(void)
 {
    asm volatile ("sfence");
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c
index d005135..32ad3c2 100644
--- a/src/southbridge/intel/bd82x6x/early_thermal.c
+++ b/src/southbridge/intel/bd82x6x/early_thermal.c
@@ -6,21 +6,6 @@
 #include "cpu/intel/model_206ax/model_206ax.h"
 #include <cpu/x86/msr.h>

-static void write8p(uintptr_t addr, uint8_t val)
-{
-	write8((uint8_t *)addr, val);
-}
-
-static void write16p(uintptr_t addr, uint16_t val)
-{
-	write16((uint16_t *)addr, val);
-}
-
-static uint16_t read16p(uintptr_t addr)
-{
-	return read16((uint16_t *)addr);
-}
-
 /* Temporary address for the thermal BAR */
 #define TBARB_TEMP 0x40000000