Change in coreboot[master]: mb/google/dedede/var/driblee: Configure audio setting

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56999 )

Change subject: mb/google/dedede/var/driblee: Configure audio setting
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mb/google/dedede/var/driblee: Configure audio setting

Update the combination audio CS42L42 and amp. MAX98360.

BUG=b:195619349, b:191732473
BRANCH=keeby
TEST=FW_NAME="driblee" emerge-keeby coreboot

Signed-off-by: Frank Wu 
Change-Id: I264c680ed5638b71c912253a38c27152a9015d4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56999
Tested-by: build bot (Jenkins) 
Reviewed-by: EricR Lai 
---
M src/mainboard/google/dedede/Kconfig.name
M src/mainboard/google/dedede/variants/driblee/overridetree.cb
2 files changed, 26 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  EricR Lai: Looks good to me, approved

diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name
index 3f3adaa..a55f189 100644
--- a/src/mainboard/google/dedede/Kconfig.name
+++ b/src/mainboard/google/dedede/Kconfig.name
@@ -177,6 +177,7 @@
    bool "-> Driblee"
    select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
    select BASEBOARD_DEDEDE_LAPTOP
+	select DRIVERS_GENERIC_MAX98357A

config BOARD_GOOGLE_GOOEY
    bool "Gooey"
diff --git a/src/mainboard/google/dedede/variants/driblee/overridetree.cb b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
index cef163f..4b0987f 100644
--- a/src/mainboard/google/dedede/variants/driblee/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
@@ -86,11 +86,36 @@
    	device pci 15.1 off end # I2C 1
    	device pci 15.2 off end # I2C 2
    	device pci 15.3 off end # I2C 3
+		device pci 19.0 on
+			chip drivers/i2c/cs42l42
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H16)"
+				register "ts_inv" = "true"
+				register "ts_dbnc_rise" = "RISE_DEB_1000_MS"
+				register "ts_dbnc_fall" = "FALL_DEB_0_MS"
+				register "btn_det_init_dbnce" = "100"
+				register "btn_det_event_dbnce" = "10"
+				register "bias_lvls[0]" = "15"
+				register "bias_lvls[1]" = "8"
+				register "bias_lvls[2]" = "4"
+				register "bias_lvls[3]" = "1"
+				register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW"
+				register "hs_bias_sense_disable" = "true"
+				device i2c 48 on end
+			end
+		end #I2C 4
    	device pci 1e.2 off end # GSPI 0
    	device pci 1f.0 on
    		chip drivers/pc80/tpm
    			device pnp 0c31.0 on end # Discrete TPM
    		end # chip drivers/pc80/tpm
    	end # PCH eSPI
+		device pci 1f.3 on
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98360A""
+				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
+				device generic 0 on end
+			end
+		end # Intel HDA
    end
 end