[M] Change in coreboot[master]: drivers/smbus: smbus console driver

[Ahamed Husni (Code Review)]

Ahamed Husni has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67339 )

Change subject: drivers/smbus: smbus console driver
......................................................................

drivers/smbus: smbus console driver

Change-Id: Ife77fb2c3e1cc77678a4972701317d50624ceb95
Signed-off-by: Husni Faiz 
---
M src/console/Kconfig
A src/drivers/smbus/i2c_smbus_console.c
A src/include/console/i2c_smbus.h
3 files changed, 84 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/67339/1

diff --git a/src/console/Kconfig b/src/console/Kconfig
index 479b7f5..4f2abb3 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -297,6 +297,34 @@
      value (128K or 0x20000 bytes) is large enough to accommodate
      even the BIOS_SPEW level.

+config CONSOLE_I2C_SMBUS
+	bool "SMBus console output"
+	default n
+	depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS
+	help
+	  Send coreboot debug output to the SMBus
+
+	  The output can be read with an I2C slave device connected the SMBus.
+
+if CONSOLE_I2C_SMBUS
+	comment "Set logging device address and data register address"
+
+config CONSOLE_I2C_SMBUS_SLAVE_ADDRESS
+	hex "I2C slave address of the logging device"
+	default 0x48
+	depends on CONSOLE_I2C_SMBUS
+	help
+	  I2C address of the device which logs the data.
+
+config CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER
+	hex "Data register address of the I2C logging device"
+	default 0x00
+	depends on CONSOLE_I2C_SMBUS
+	help
+	  This an 8-bit data register.
+
+endif # CONSOLE_I2C_SMBUS
+
 config CONSOLE_QEMU_DEBUGCON
    bool "QEMU debug console output"
    depends on CPU_QEMU_X86
diff --git a/src/drivers/smbus/i2c_smbus_console.c b/src/drivers/smbus/i2c_smbus_console.c
new file mode 100644
index 0000000..367191a
--- /dev/null
+++ b/src/drivers/smbus/i2c_smbus_console.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/i2c_smbus.h>
+#include <device/smbus_host.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void i2c_smbus_console_init(void)
+{
+#if (CONFIG(CONSOLE_I2C_SMBUS) && (ENV_ROMSTAGE || ENV_BOOTBLOCK))
+	early_pch_init();
+#endif
+}
+
+void i2c_smbus_console_tx_byte(unsigned char c)
+{
+#if (CONFIG(CONSOLE_I2C_SMBUS) && (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE))
+	do_smbus_write_byte(CONFIG_FIXED_SMBUS_IO_BASE, \
+		CONFIG_CONSOLE_I2C_SMBUS_SLAVE_ADDRESS, \
+		CONFIG_CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER, c);
+#endif
+}
diff --git a/src/include/console/i2c_smbus.h b/src/include/console/i2c_smbus.h
new file mode 100644
index 0000000..344d961
--- /dev/null
+++ b/src/include/console/i2c_smbus.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CONSOLE_I2C_SMBUS_H
+#define CONSOLE_I2C_SMBUS_H
+
+#include <stdint.h>
+
+void i2c_smbus_console_init(void);
+void i2c_smbus_console_tx_byte(unsigned char c);
+
+#define __CONSOLE_SMBUS_ENABLE__	(CONFIG(CONSOLE_I2C_SMBUS) && \
+	(ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE))
+
+#if __CONSOLE_SMBUS_ENABLE__
+static inline void __i2c_smbus_console_init(void)	{ i2c_smbus_console_init(); }
+static inline void __i2c_smbus_console_tx_byte(u8 data)
+{
+	i2c_smbus_console_tx_byte(data);
+}
+#else
+static inline void __i2c_smbus_console_init(void)	{}
+static inline void __i2c_smbus_console_tx_byte(u8 data)	{}
+#endif /* __CONSOLE_SMBUS_ENABLE__ */
+
+#endif /* CONSOLE_I2C_SMBUS_H */