[M] Change in coreboot[master]: mb/intel/mtlrvp: Enable ACPI support for Type-C ports

[Harsha B R (Code Review)]

Harsha B R has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72789 )

Change subject: mb/intel/mtlrvp: Enable ACPI support for Type-C ports
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mb/intel/mtlrvp: Enable ACPI support for Type-C ports

This patch adds ACPI support for Type-C ports.

BUG=b:224325352
BRANCH=None
Test=Able to build and boot MTLRVP. Verify SSDT for the correspodning
entry,
_SB.PCI0.PMC.MUX.CON0 under Device (CON0)
_SB.PCI0.PMC.MUX.CON1 under Device (CON1)
_SB.PCI0.PMC.MUX.CON2 under Device (CON2)
_SB.PCI0.PMC.MUX.CON3 under Device (CON3)

Signed-off-by: Harsha B R 
Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811
---
M src/mainboard/intel/mtlrvp/Kconfig
M src/mainboard/intel/mtlrvp/dsdt.asl
M src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb
3 files changed, 51 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/72789/1

diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index 945aa2e..3468ac9 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -13,6 +13,7 @@

config BOARD_INTEL_MTLRVP_P_EXT_EC
    select BOARD_INTEL_MTLRVP_COMMON
+	select DRIVERS_INTEL_PMC

if BOARD_INTEL_MTLRVP_COMMON

diff --git a/src/mainboard/intel/mtlrvp/dsdt.asl b/src/mainboard/intel/mtlrvp/dsdt.asl
index d253617..a367bbb 100644
--- a/src/mainboard/intel/mtlrvp/dsdt.asl
+++ b/src/mainboard/intel/mtlrvp/dsdt.asl
@@ -22,6 +22,7 @@
    	{
    		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
    		#include <soc/intel/meteorlake/acpi/southbridge.asl>
+			#include <soc/intel/meteorlake/acpi/tcss.asl>
    	}
    }

diff --git a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb
index b08d7ca..26b833f 100644
--- a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb
@@ -3,8 +3,36 @@
    device domain 0 on
    	device ref soc_espi on
    		chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
    			device pnp 0c09.0 on end
    		end
    	end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port3 as usb2_port
+						use tcss_usb3_port3 as usb3_port
+						device generic 2 alias conn2 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port4 as usb2_port
+						use tcss_usb3_port4 as usb3_port
+						device generic 3 alias conn3 on end
+					end
+				end
+			end
+		end
    end
 end