Change in coreboot[master]: soc/intel/alderlake: Correct TCSS XHCI Port status offset

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Subrata Banik, Balaji Manigandan, Deepti Deshatty, Patrick Rudolph.
Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Deepti Deshatty, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/55230

to look at the new patch set (#3).

Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset
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soc/intel/alderlake: Correct TCSS XHCI Port status offset

The patch corrects TCSS XHCI Port status offset. The information is
captured from the ADL-P Processor EDS Volume 2b of 2(DOC ID:619503).

BUG=None
TEST=Verified boot on Brya

Signed-off-by: Sridhar Siricilla 
Change-Id: I20c77d78f52277a9a979e11303cdb6cdabae7c59
---
M src/soc/intel/alderlake/xhci.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/55230/3