Change in coreboot[master]: cpu/amd: Misc. formatting improvements

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/27935

Change subject: cpu/amd: Misc. formatting improvements
......................................................................

cpu/amd: Misc. formatting improvements

Remove for() braces from around single lines.  Remove extra blank lines.

Change-Id: I329ac03365e51799581c56eed27ee54de6826f14
Signed-off-by: Marshall Dawson 
---
M src/cpu/amd/agesa/family12/model_12_init.c
M src/cpu/amd/agesa/family14/model_14_init.c
M src/cpu/amd/agesa/family15tn/model_15_init.c
M src/cpu/amd/agesa/family16kb/model_16_init.c
M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
M src/cpu/amd/pi/00660F01/model_15_init.c
M src/cpu/amd/pi/00730F01/model_16_init.c
7 files changed, 5 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/27935/1

diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index afdfb3b..93aecad 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -54,9 +54,8 @@
    /* zero the machine check error status registers */
    msr.lo = 0;
    msr.hi = 0;
-	for (i = 0; i < 5; i++) {
+	for (i = 0; i < 5; i++)
    	wrmsr(MC0_STATUS + (i * 4), msr);
-	}

enable_cache();

diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 257f81f..ffb856a 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -77,9 +77,8 @@
    /* zero the machine check error status registers */
    msr.lo = 0;
    msr.hi = 0;
-	for (i = 0; i < 6; i++) {
+	for (i = 0; i < 6; i++)
    	wrmsr(MC0_STATUS + (i * 4), msr);
-	}

/* Enable the local CPU APICs */
    setup_lapic();
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 1e0375f..8ae184e 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -74,9 +74,8 @@
    /* zero the machine check error status registers */
    msr.lo = 0;
    msr.hi = 0;
-	for (i = 0; i < 6; i++) {
+	for (i = 0; i < 6; i++)
    	wrmsr(MC0_STATUS + (i * 4), msr);
-	}

/* Enable the local CPU APICs */
    setup_lapic();
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index 9909793..92c7bca 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -72,9 +72,8 @@
    /* zero the machine check error status registers */
    msr.lo = 0;
    msr.hi = 0;
-	for (i = 0; i < 6; i++) {
+	for (i = 0; i < 6; i++)
    	wrmsr(MC0_STATUS + (i * 4), msr);
-	}

/* Enable the local CPU APICs */
    setup_lapic();
@@ -99,7 +98,6 @@
    msr.hi &= ~(1 << (46 - 32));
    wrmsr(NB_CFG_MSR, msr);

-
    /* Write protect SMM space with SMMLOCK. */
    msr = rdmsr(HWCR_MSR);
    msr.lo |= (1 << 0);
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index 61eb813..74d4673 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -111,9 +111,8 @@
    /* zero the machine check error status registers */
    msr.lo = 0;
    msr.hi = 0;
-	for (i = 0; i < 5; i++) {
+	for (i = 0; i < 5; i++)
    	wrmsr(MC0_STATUS + (i * 4), msr);
-	}

enable_cache();

diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
index 24c2aea..0540a72 100644
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ b/src/cpu/amd/pi/00660F01/model_15_init.c
@@ -86,7 +86,6 @@
    for (i = 0; i < 6; i++)
    	wrmsr(MC0_STATUS + (i * 4), msr);

-
    /* Enable the local CPU APICs */
    setup_lapic();

diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index b9e0185..3ae841d 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -71,7 +71,6 @@
    for (i = 0; i < 6; i++)
    	wrmsr(MC0_STATUS + (i * 4), msr);

-
    /* Enable the local CPU APICs */
    setup_lapic();

@@ -95,7 +94,6 @@
    msr.hi &= ~(1 << (46 - 32));
    wrmsr(NB_CFG_MSR, msr);

-
    /* Write protect SMM space with SMMLOCK. */
    msr = rdmsr(HWCR_MSR);
    msr.lo |= (1 << 0);