Hello Furquan Shaikh, Nick Vaccaro,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39329
to review the following change.
Change subject: soc/intel/tigerlake: allow override of clock sources ......................................................................
soc/intel/tigerlake: allow override of clock sources
Pass PcieClkSrcUsage and PcieClkSrcClkReq overrides to fsp.
BUG=b:144887381, b:142961277 BRANCH=none TEST='emerge-volteer coreboot chromeos-bootimage', flash to device, verify that we can boot to kernel on NVME.
Change-Id: I90c86a6af80baf6b9aff4a0001dd20a84988ac56 Signed-off-by: Nick Vaccaro nvaccaro@google.com Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreb... Commit-Queue: Furquan Shaikh furquan@google.com Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39329/1
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index f0f3b4c..b2d3099 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -45,6 +45,11 @@
memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, sizeof(config->PcieClkSrcUsage)); + memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, + sizeof(config->PcieClkSrcClkReq)); + + memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, + sizeof(config->PcieClkSrcUsage));
for (i = 0; i < CONFIG_MAX_PCIE_CLOCKS; i++) { if (config->PcieClkSrcUsage[i] == 0)
Jes Klinke has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39329 )
Change subject: soc/intel/tigerlake: allow override of clock sources ......................................................................
Patch Set 1:
First attempt at upstreaming a tiny patch by Nick from the Intel private repository.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39329 )
Change subject: soc/intel/tigerlake: allow override of clock sources ......................................................................
Patch Set 1: Code-Review-1
(2 comments)
This change is not really required.
https://review.coreboot.org/c/coreboot/+/39329/1/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39329/1/src/soc/intel/tigerlake/rom... PS1, Line 46: memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, : sizeof(config->PcieClkSrcUsage)); This is exactly the same as lines 51-52 that you are adding. It was done as part of: https://review.coreboot.org/c/coreboot/+/37960/28/src/soc/intel/tigerlake/ro...
https://review.coreboot.org/c/coreboot/+/39329/1/src/soc/intel/tigerlake/rom... PS1, Line 59: memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, : sizeof(config->PcieClkSrcClkReq)); This is exactly the same as lines 48-49 above. It was done as part of: https://review.coreboot.org/c/coreboot/+/38285
Jes Klinke has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39329 )
Change subject: soc/intel/tigerlake: allow override of clock sources ......................................................................
Patch Set 1:
Sorry for wasting your time with this. I was so consumed by wrangling with git, that I did not pay any attention to the content of the patch.
I will mark this CL as abandoned, when I figure out how.
Jes Klinke has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39329 )
Change subject: soc/intel/tigerlake: allow override of clock sources ......................................................................
Abandoned
Code is already in the repository, from other commits.
-
Furquan Shaikh (Code Review) -
Jes Klinke (Code Review)