Change in coreboot[master]: mb/google/sarien: Enable WWAN detection

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/29430

Change subject: mb/google/sarien: Enable WWAN detection
......................................................................

mb/google/sarien: Enable WWAN detection

WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF#
set to high after at least 10 ms, so force RESET#(GPP_D21) to low at
bootblock stage to match the sequence.

BUG=N/A
TEST=Boot up Sarien/Arcada board, check WWAN get detected as USB
devices through lsusb.

Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133
Signed-off-by: Lijian Zhao 
---
M src/mainboard/google/sarien/variants/arcada/gpio.c
M src/mainboard/google/sarien/variants/sarien/gpio.c
2 files changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/29430/1

diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c
index 86da3ec..22db02f 100644
--- a/src/mainboard/google/sarien/variants/arcada/gpio.c
+++ b/src/mainboard/google/sarien/variants/arcada/gpio.c
@@ -234,6 +234,7 @@
 /* I2C4_SCL */		PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
 /* DMIC_DATA1 */	PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
    			 EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
+/* SPI1_IO2 */		PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */
 /* CPU_GP0 */		PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
 /* SATALED# */		PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
 /* DDPD_HPD2 */		PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c
index 3656afb..e203bcc 100644
--- a/src/mainboard/google/sarien/variants/sarien/gpio.c
+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c
@@ -234,6 +234,7 @@
 /* I2C4_SCL */		PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
 /* DMIC_DATA1 */	PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
    			 EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
+/* SPI1_IO2 */		PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */
 /* CPU_GP0 */		PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
 /* SATALED# */		PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */
 /* DDPD_HPD2 */		PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */